EDA技术与VHDL课后答案(第3版)潘松 黄继业

第3章 VHDL基础 习题 3-1 如图所示 3-2 程序： IF_THEN语句 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 S PORT ( s1,s0 : IN STD_LOGIC_VECTOR ; a,b,c,d : IN STD_LOGIC ; y : OUT STD_LOGIC ) ; END ENTITY mux21 ; ARCHITECTURE one OF mux21 IS BEGIN PROCESS ( s0,s1,a,b,c,d ) BEGIN IF s1=0 AND s0=0 THEN y=a ; ELSIF s1=0 AND s0=1 THEN y=b ; ELSIF s1=1 AND s0=0 THEN y=c ; ELSIF s1=1 AND s0=1 THEN y=d ; ELSE y=NULL ; END IF ; END PROCESS ; END ARCHITECTURE one ; CASE 语句 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 IS PORT ( s1,s0 : IN STD_LOGIC_VECTOR ; a,b,c,d : IN STD_LOGIC ; y : OUT STD_LOGIC ) ; END ENTITY mux21 ; ARCHITECTURE two OF mux21 IS SIGNAL s : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; BEGIN s y y y y NULL ; END CASE ; END PROCESS ; END ARCHITECTURE two ; 3-3 程序： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY MUXK IS PORT ( s0,s1 : IN STD_LOGIC ; a1,a2,a3 : IN STD_LOGIC ; outy : OUT STD_LOGIC ) ; END ENTITY MUXK ; ARCHITECTURE double OF MUXK IS SIGNAL tmp : STD_LOGIC ; -内部连接线 BEGIN p_MUX21A_u1 : PROCESS ( u1_s, u1_a, u1_b, u1_y ) SIGNAL u1_s, u1_a, u1_b, u1_y : STD_LOGIC ; BEGIN IF u1_s=0 THEN u1_y= u1_a ; ELSIF u1_y= u1_b ; ELSE u1_y= NULL ; END IF ; END PROCESS p_ MUX21A_u1 ; p_ MUX21A_u2 : PROCESS ( u2_s, u2_a, u2_b, u2_y ) SIGNAL u2_s, u2_a, u2_b, u2_y : STD_LOGIC ; BEGIN IF u2_s=0 THEN u2_y= u2_a ; ELSIF u2_y= u2_b ; ELSE u2_y= NULL ; END IF ; END PROCESS p_ MUX21A_u2 ; u1_s= s0 ; u1_a= a2 ; u1_b= a3 ; tmp= u1_y ; u2_s=s1 ; u2_a= a1 ; u2_b= tmp; outy = u2_y ; END ARCHITECTURE double ; 3-4 程序： （1）1位半减器 1位半减器的设计选用（2）图，两种表达方式： 一、 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY h_suber IS PORT ( x,y : IN STD_LOGIC ; s_out ,diff : OUT STD_LOGIC ) ; END ENTITY h_suber ; ARCHITECTURE fhd1 OF h_suber IS BEGIN diff=x XOR y ; s_out= ( NOT a ) AND b ; END ARCHITECTURE fhd1 ; 二、 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY h_suber IS PORT ( x,y : IN STD_LOGIC ; s_out ,diff : OUT STD_LOGIC ) ; END ENTITY h_suber ; ARCHITECTURE fhd1 OF h_suber IS SIGNAL s : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; BEGIN s s_out =0 ; diff s_out =1 ; diff s_out =0 ; diff s_out =0 ; diff NULL ; END CASE ; END PROCESS ; END ARCHITECTURE fhd1 ; 或门逻辑描述： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY or IS PORT ( a,b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END ENTITY or ; ARCHITECTURE one OF or IS BEGIN cx, y=y, diff=d, s_out=e ) ; u2 : h_suber PORT MAP ( x=d, y=sub_in, diff=diffr, s_out=f ) ; u3 : or PORT MAP ( a=f, b=e, c=sub_out ) ; END ARCHITECTURE fhd1 ; （2）8位减法器： f_subersub_in x y sub_outdiffr0x0y0f_subersub_in x y sub_outdiffr1x1y1f_subersub_in x y sub_outdiffr2x2y2f_subersub_in x y sub_outdiffr3x3y3f_subersub_in x y sub_outdiffr4x4y4f_subersub_in x y sub_outdiffr5x5y5f_subersub_in x y sub_outdiffr6x6y6f_subersub_in x y sub_outdiffr7x7y7 sub_outa b cde f gu0 u1 u2 u3u4 u5 u6 u7 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY 8f_suber IS PORT ( x0,x1,x2,x3,x4,x5,x6,x7 : IN STD_LOGIC ; y0,y1,y2,y3,y4,y5,y6,y7 : IN STD_LOGIC ; sub_in : IN STD_LOGIC ; sub_out : OUT STD_LOGIC ; diffr0,diffr1,diffr2,diffr3 : OUT STD_LOGIC ; diffr4,diffr5,diffr6,diffr7 : OUT STD_LOGIC ) ; END ENTITY 8f_suber ; ARCHITECTURE 8fhd1 OF 8f_suber IS COMPONENT f_suber IS PORT ( x,y,sub_in : IN STD_LOGIC ; sub_out ,diffr : OUT STD_LOGIC ) ; END COMPONENT f_suber ; SIGNAL a,b,c,d,e,f,g : STD_LOGIC ; BEGIN u0 : f_suber PORT MAP ( x=x0, y=y0, sub_in=, sub_out=a, diff=diff0 ) ; u1 : f_suber PORT MAP ( x=x1, y=y1, sub_in=a, sub_out=b, diff=diff1 ) ; u2 : f_suber PORT MAP (x=x2, y=y2, sub_in=b, sub_out=c, diff=diff2 ) ; u3 : f_suber PORT MAP (x=x3, y=y3, sub_in=c, sub_out=d, diff=diff3 ) ; u4 : f_suber PORT MAP (x=x4, y=y4, sub_in=d, sub_out=e, diff=diff4 ) ; u5 : f_suber PORT MAP (x=x5, y=y5, sub_in=e, sub_out=f, diff=diff5 ) ; u6 : f_suber PORT MAP (x=x6, y=y6, sub_in=f, sub_out=g, diff=diff6 ) ; u7 : f_suber PORT MAP (x=x7, y=y7, sub_in=g, sub_out= sub_out, diff=diff7 ) ; END ARCHITECTURE 8fhd1 ; 3-5 程序： 或非门逻辑描述： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY nor IS PORT ( d,e : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END ENTITY nor ; ARCHITECTURE one OF nor IS BEGIN f c, e=CL, f=a ) ; u1 : DFF1 PORT MAP ( CLK=CLK0, D=a, Q=b ) ; u2 : not PORT MAP ( g=b, g=c, h=OUT1 ) ; END ARCHITECTURE one ; 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 程序1： SIGNAL A,EN : STD_LOGIC ; PROCESS ( A, EN ) VARIABLE B : STD_LOGIC ; BEGIN IF EN = 1 THEN B := A ; END IF ; END PROCESS ; 程序2： ARCHITECTURE one OF sample IS VARIABLE a,b,c : BEGIN c := a+b ; END ARCHITECTURE one ; 程序3： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 IS PORT ( a,b : IN STD_LOGIC ; sel : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END ENTITY mux21 ; ARCHITECTURE one OF mux21 IS BEGIN IF sel = 0 THEN c=a ; ELSE c=b ; END IF ; END ARCHITECTURE one ; 第4章 Quartus II使用方法 习题 4-1 第5章 VHDL状态机 习题 5-1 例5-4（两个进程）： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY MOORE1 IS PORT ( DATAIN : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; CLK,RST : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ) ; END ENTITY MOORE1 ; ARCHITECTURE behav OF MOORE1 IS TYPE ST_TYPE IS ( ST0,ST1,ST2,ST3,ST4 ) ; SIGNAL C_ST ,N_ST : ST_TYPE ; BEGIN REG : PROCESS ( RST ,CLK ) BEGIN IF RST=1 THEN C_ST=ST0; Q=”0000”; ELSIF CLK EVENT AND CLK=1 THEN C_ST IF DATAIN = “10” THEN N_ST = ST1 ; ELSE N_ST = ST0 ; END IF ; Q IF DATAIN = “11” THEN N_ST = ST2 ; ELSE N_ST = ST1 ; END IF ; Q IF DATAIN = “01” THEN N_ST = ST3 ; ELSE N_ST = ST0 ; END IF ; Q IF DATAIN = “00” THEN N_ST = ST4 ; ELSE N_ST = ST2 ; END IF ; Q IF DATAIN = “11” THEN N_ST = ST0 ; ELSE N_ST = ST3 ; END IF ; Q N_ST = ST0 ; END CASE ; END PROCESS ; END ARCHITECTURE behav ; 5-2 例5-5（单进程）： LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY MEALY1 IS PORT ( CLK, DATAIN ,RESET : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0 ) ) ; END ENTITY MEALY1 ; ARCHITECTURE behav OF MEALY1 IS TYPE states IS ( st0,st1,st2,st3,st4 ) ; SIGNAL STX : states ; BEGIN PROCESS ( CLK, RESET ) BEGIN IF RESET = 1 THEN STX IF DATAIN = 1 THEN STX= st1; Q=”10000” ; ELSE Q IF DATAIN = 0 THEN STX= st2; Q=”10111” ; ELSE Q IF DATAIN = 1 THEN STX= st3; Q=”10101” ; ELSE Q IF DATAIN = 0 THEN STX= st4; Q=”11011” ; ELSE Q IF DATAIN = 1 THEN STX= st0; Q=”11101” ; ELSE Q STX=st0; Q=”00000” ; END CASE ; END PROCESS ; END ARCHITECTURE behav ; 5-3 序列检测器： 要求1： 要求2： 要求3： 5-4 5-5 第6章 16位CISC CPU设计 习题 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 第7章 VHDL语句 习题 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 第8章 VHDL结构 习题 8-1 8-2 8-3 8-4 8-5 VHDL综合器支持的类型：STRING、BIT； 8-6 【例8-28】 LIBRARY IEEE ; - USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY decoder3t08 IS port ( input: IN STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ; output: OUT BIT_VECTOR ( 7 DOWNTO 0 ) ) ; END ENTITY decoder3t08 ; ARCHITECTURE behave OF decoder3t08 IS BEGIN output 显式表达； STD ：STANDARD、TEXTIO 无须显式表达； WORK ：无须显式表达，总是可见； VITAL ：VITAL_TIMING、VITAL_PRIMITIVES 8-12 8-13 8-14 8-15