锁相环原理以及倍频分频实现

锁相环原理以及倍频/分频实现A phase-locked loop (PLL) is a closed-loop frequency-control system based on the phase diffe rence between the input clock signal and the feedback clock signal of a cont rolled oscillat or. Fig ure 1 shows a simplified block diag ram of the maj or components in a PLL. The main blocks of the PLL are the phase frequency detect or (PFD), cha rge pump, loop filte r, voltage cont rolled oscillat or (VCO), and counte rs, such as a feedback counte r (M), a pr e-scale counte r (N), and post-scale counte rs(C).注锁相环是一种基于输入信号与输入信号反馈给振荡控制器的信号之间的相位差的闭环频率控制系统图 1展示了锁相环的基本原理框图。图中的PLL主要由鉴相器(PFD)，电荷泵，回路滤波器，压控振荡电 路(VCO)，计数器(反馈技术器M,预分频技术器N,后分频C).Figure 1. Block Diagram of a PLLVCO PhafiA Selection at Each PLL Output Port曽怦HlterumP & VCOLpPFDciwnPfl&t-Scal&Coiirrtere-PLLs in Alte raFPGAs align the rising edge of the refer ence input clock to a feedback clock using the PFD. The falling edges are dete rmined by the duty-cycle specified by the use r. The PFD detects the diffe rence in phase and frequency between the refer ence clock and feedback clock inputs and gene rates an “up or “down” cont rol signal based on whethe r the feedback frequency is lagging or leading the refer ence frequency. These “up” or “down” cont rol signals dete rmine whethe r the VCO needs to ope rate at a highe r or lowe r frequency, r espectively.注.Altera FPFG芯片内的PLL中，在每个参考时钟的上升沿将通过鉴相器(PFD)产生一个反馈时钟信号. 由用户指定的占空比来决定时钟的下降沿.PFD检测参考时钟与反馈时钟之间的频率差以及相位差并产 生”up”或down”的控制信号这个控制信号表征着反馈信号是超前还是落后于参考时钟信号这两种不同 的信号决定着压控振荡器(VCO)是否需要提高频率或者降低频率.The PFD outputs these “up” and “down” signals to a cha rge pump. If the cha rge pump r eceives an up signal, curr ent is dr iven into the loop filte r. Conve rsely, if it r eceives a down signal, curr ent is dr awn from the loop filte r.注.PFD产生的-up-,down”将输出给电荷泵，如果电荷泵接收到的是”up”信号,电流将进入环路滤波相反 的将从环路滤波器中吸取电流.The loop filte r conve rts these signals to a cont rol voltage that is used to bias the VCO. Based on the cont rol voltage, the VCO oscillates at a highe r or lowe r frequency, which affects the phase and frequency of the feedback clock. If the PFD pr oduces an up signal, then the VCO frequency inc reases. A down signal dec reases the VCO frequency. The VCO stabilizes once the refer ence clock and the feedback clock have the same phase and frequency. The loop filte r filte rs out jitte r by r emoving glitches from the cha rge pump and pr eventing voltage ove r-shoot.注环路滤波将”up”down ”信号准换为压控信号传递给压控振荡器并控制压控振荡器的振荡频率如果 PFD产生的是”up”信号,VCO将提高振荡频率，相反减少振荡频率直到参考时钟信号与反馈时钟信号具有 相同的振荡频率以及相位.环路滤波器将滤除电荷泵产生的噪声振荡并且防止电压过载.When the refer ence clock and the feedback clock are aligned, the PLL is conside red locked. To find reasons why a PLL may lose lock, see Why Does My PLL Lose Lock?注当参考频率与反馈频率一致的时候,PLL被称为锁定.A divide counte r (M) is inse rted in the feedback loop to inc rease the VCO frequency above the input refer ence frequency. VCO frequency (FVCO) is equal to (M) times the input refer ence clock (F ). The PFD input refer ence clock (F ) is equal to the input clock (R.) divided by the pr e-scale counte r (N). Therefore, the feedback clock (FB) applied to one input of the PFD is locked to the F Ithat is applied to the othe r input of the PFD. The VCO output feeds post-scale counte rs which allow a numbe r of har monically r elated frequencies to be pr oduced within the PLL.注反馈回路上插入一个除法器(M)可以在参考时钟频率的基础上实现M倍频.PFD的输入频率等于输入频 率/N.The output frequency of the PLL is equal to the VCO frequency (FVCO) divided by the post-scale counte r (C).In the form of equations: fref = Fin / N Fvco = Fref x M = Fin x M/N Fout = Fvco / C =(Fref x M) / C =(Fin x M) / (N x C)whe re: fvco = VCO frequency fin = input frequency fref = refer ence frequency fout = output frequency M = counte r (multiplie r), part of the clock feedback path N = counte r (divide r), part of the input clock refer ence pathC = postscale counter (divider)