汽车行驶记录仪论文：汽车行驶记录仪的研究与实现

汽车行驶记录仪论文：汽车行驶记录仪的研究与实现【中文摘要】随着社会经济的发展,现代交通工具发挥着越来越重要的作用,但是日益增多的交通事故也给人们带来了难以计数的人员伤亡和财产损失。汽车行驶记录仪是对车辆行驶速度、时间、里程以及有关车辆行驶的其它状态信息进行记录存储并可以通过接口实现数据输出的数字式电子记录装置。记录仪不仅可以遏止交通违章、约束驾驶员不良驾驶习惯,而且可以有效地预防道路交通事故的发生,并为执法人员进行事故的分析、处理提供科学、忠实的原始数据,在交通运输管理中发挥着十分重要的作用。在嵌入式技术被广泛运用的今天,我国现有的汽车记录仪仍然多是以单片机作为处理器,功能单一。本论文在参考了国内外多种不同结构,不同领域的汽车行驶记录仪的设计与研究的基础上,将现今领先的FPGA技术应用在传统的汽车行驶记录仪上。高速、低功耗的新型FPGA集成了中央处理器、数字处理器内核,可进行软硬件协同设计,从而缩短设计时间,提高汽车行驶记录仪的集成性、稳定性和灵活性。本论文首先分析了国内外汽车行驶记录仪的相关背景和现状,根据汽车行驶记录仪的国家标准及其系统性能指标要求,提出了一种基于FPGA的汽车行驶记录仪系统的设计方案。结合本课题设计方案,确定了系统设计的主要构架,初步提出了系统设计预期的性能指标参数。系统开发采用Altera公司FPGA技术的硬件开发平台和软件开发环境。其次,根据系统的总体方案,详细进行了系统的硬件和软件设计。设计突出了SOPC技术的优点,在硬件部分中,设计了汽车行驶记录仪的供电及复位模块、信号采集模块、存储模块、显示模块、按键模块和通信模块等各个部分的电路结构。在软件部分中,利用Quartus实现系统硬件电路及软件平台的搭建,设计采用自顶向下的模块化开发流程,实现系统各个功能模块以及系统与外设各个连接接口的功能模块设计；同时详细说明了Nios软核处理器的开发过程及本系统的软件设计流程和调试代码；并且对该系统进行综合、布局布线,随后进行了系统综合后的时序仿真；接着将生成的配置文件下载到目标板实现,进行系统的硬件调试和验证。最后,总结自己在本次系统设计中的工作,针对本系统核心FPGA良好的可重构特性和Nios工软核处理器易完成系统维护和升级换代的特性提出对本系统未来的展望。系统设计充分发挥了Nios软核处理器及SOPC Builder提供的IP核功能,简化硬件电路设计,使得开发精力集中在系统功能实现上,缩短了系统开发周期,提高了设计效率；利用FPGA的可编程特性,使得系统的电路设计具有良好的可移植性和可重构性,便于系统的扩展和升级,增强了系统的灵活性和完整性。实验测试结果表明,系统硬件及软件运行稳定,测试结果各项指标基本满足系统预期的性能指标要求,且该系统开发成本低,系统功耗小,具有极强的市场竞争力。【英文摘要】Accompany rapid development of society and economy, modem transports are playing more and more important roles. However, increasing traffic accidents cause countless casualties and property damage. Vehicle Traveling Data Recorder is a digital electronic recorder which can collect and store vehicles running velocity, time, distance and other state information related. It can also transmit data via interface. Vehicle Traveling Data Recorder can hold out traffic violations, restrict drivers from bad drive habit, prevent traffic accidents from happening, provide scientific, veritable origin datum for tipstaffs to analyze and dispose accidents. It plays a very important role in transportation management.Nowadays, embedded technology is widely used in various fields. In our country, Vehicle Traveling Data Recorder is still using a single-chip processor with a unitary function. In this paper, we reference to a variety of different structures at home and abroad. Based on the design and research in different areas of the Vehicle Traveling Data Recorder, we present leading FPGA technology in traditional Vehicle Traveling Data Recorder. High-speed and low-power FPGA, with integration of new central processor and digital processor core, can carry out hardware and software co-design, and then reduce design time and improve integration, stability and flexibility of vehicle traveling data recorder.In this paper, we first introduce and analyze background and status of domestic and foreign Vehicle Traveling Data Recorder. Combine with project design, expected indicators of design performance parameters are preliminary proposed. And base on performance indicators, we determine main framework of system design. According to national standards of Vehicle Traveling Data Recorder and its expected performance, we propose a FPGA-based Vehicle Traveling Data Recorder design program. Hardware platforms and software development environment of this work is developed with FPGA technology by Altera company.Secondly, we descript overall system design, system hardware and software design in detail. The design highlights advantages of SOPC technology, builds hardware and software platform in internal implementation of a single FPGA, achieve development processes of each functional module of the system and interface between the system and each peripheral. In the part about software, we first describe flow of software system, and then describe the systems Niossoft-core processors and its development process in detail.Finally, we record the process of hardware and software adjustment and performance testing, analysis and optimize the results of experiment, and put forward prospects according to the test results.Design of the system brings fully functional IP cores which provided by SOPC Builder and NiosII soft processor. Therefore, we simplify circuit design of the systems hardware, make productive development focus on system function and algorithm design, improve design efficiency. Using FPGA characteristics of programming, we bring flexibility of circuit design and reconstruction of algorithm, let the system has good portability, and reveal scalability of the system. Experimental results show that the system operating stability. And testing results also show that each index of the system meets the basic requirements. And low-cost and low-power consumption of development of this system has strong competitiveness in the market.【关键词】汽车行驶记录仪 FPGA SOPC Nios【英文关键词】Vehicle Traveling Data Recorder FPGA SOPC Nios【目录】汽车行驶记录仪的研究与实现摘要8-10ABSTRACT10-11第1章 绪论12-181.1 课题的选题背景与意义12-131.2 国内外发展现状13-151.2.1 国外发展现状13-141.2.2 国内发展现状14-151.2.3 未来发展动态151.3 汽车行驶记录仪的功能和技术指标15-161.4 论文的主要研究内容16-171.5 本章小结17-18第2章 系统总体设计18-302.1 系统总体方案设计18-192.2 汽车行驶记录仪的基本功能分析192.3 系统核心模块FPGA的开发环境19-262.3.1 FPGA简介202.3.2 Quartus开发环境20-222.3.3 SOPC技术22-232.3.4 SOPC Builder开发环境23-242.3.5 Nios处理器24-252.3.6 Avalon总线系统25-262.4 系统SOPC方案的选择26-272.5 系统SOPC设计流程27-282.6 本章小结28-30第3章 系统硬件设计30-423.1 系统主电路图设计30-313.2 电源模块设计31-333.3 信号采集模块设计33-343.4 FLASH接口电路设计34-353.5 SDRAM接口电路设计35-363.6 数据通信模块设计36-373.7 液晶显示模块LCD接口电路设计37-383.8 输入开关按键电路设计38-393.9 JTAG接口电路设计39-403.10 RESET模块电路设计403.11 本章小结40-42第4章 系统软件设计42-644.1 创建QUARTUS 工程42-434.2 NIos内核硬件系统的组建43-484.3 QUARTUS 工程顶层的建立48-524.4 编译并下载设计52-534.5 NIOS IDE53-544.6 程序流程图54-554.7 时间信息的设置和获取55-564.8 LCD液晶显示程序设计56-574.9 RS-232串口通信程序设计574.10 FLASH信息存储程序设计57-584.11 系统仿真和调试58-624.12 本章小结62-64结论与展望64-66附录66-76参考文献76-78攻读学位期间发表的学术论文78-80致谢80-81学位论文评阅及答辩情祝表81