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基于FPGA控制的LED汉字滚动显示器设计2 硬件原理图整个电路由五大部分组成：时钟计数模块GEL_CLK，存储汉字字模的ROM模块ROMZI，数据分配器模块MUX，移位模块YW及显示模块XIANSH-I。时钟计数模块用于产生整个电路所需要的时钟及其对时钟的计数值，例如：移位时钟CLK YW，移位计数器CNT YW，字计数器CNT WORD，显示扫描计数器CNT SM。ROMZI模块是由Qualtus中的LPM 1PORT ROM定制成，用来存储8个待显示的汉字。MUX模块用于在扫描时钟及扫描计数器的作用下，从ROM中读出一个汉字的8个行字模信息，送给移位模块YW，YW模块在移位时钟及移位计数器作用下，根据SELECT信号选择对读出的字模信息，进行相应的移位(左移、右移、上移、下移)后，最后送显示模块DISP驱动LED点阵显示汉字。原理图如图2所示。32 ROMZI模块利用LPM参数化模块库中单口ROM，利用Qualtus中的MegaWizard Plug-In Manager定制而成，定制前首先要制作LPM ROM初始化文件，其中存储待显示汉字的字模数据，然后按照LPM MegaWizardPlug-In Manager的向导提示，结合设计要求进行定制。图3为所定制ROM中的初始化汉字“元旦生日开心快乐”的字型码。数据分配模块MUX要求能在8个时钟作用下，从ROM中读出一行(一个汉字的8个字型码)分别送到数据分配器中的WLlWL8输出端。图4为数据分配模块在扫描时钟作用下读取的字模数据，比较图3和图4可知，仿真结果正确，能满足题目要求。33 移位模块YW移位模块YW是整个设计的核心，行扫描实现左移，是通过每来一个移位时钟，将每一行的字模按位左移一位，扫描时钟到来时送出移位后的新字模。通过8次移位，可将一个汉字移出点阵平面，按类似的道理，也可以将一个汉字经8次移位后移进点阵平面。本例(图2)中，CNT YW为移位时钟的计数值，以WLlWL8为欲显示汉字的原始字模，L10L80为移位后从列上送出的8行显示字模信息，LLlLL8为8个原始字模信息未送出位的暂存信号。设计中需要16个移位时钟，通过前8个时钟将WLlWL8字模移进LED点阵平面，再经后8个时钟，将汉字又一位一位地移出。移位设计参考文献中有关移位寄存器的设计，分计数值为“0000和非0000两部分处理，对第一行字模的处理为：其他行可按相同方法处理，具体参见如下的程序：library IEEE;use IEEE.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity memtest isport (rst : in std_logic;clk : in std_logic;den : in std_logic;-serial input enablerxd : in std_logic;-serial input dataouten : in std_logic;- output data requestrdmem : out std_logic;-read memorywrmem : out std_logic;- write memorycsmem : out std_logic;- chip enable memorymemdata: inout std_logic_vector(7 downto 0);- memory data interfacememaddr: out std_logic_vector(2 downto 0);- memory addressdataout: out std_logic_vector(7 downto 0);-data outputdataclkout: out std_logic -data output sync clk );end memtest;architecture behav of memtest is constant s0 :std_logic_vector(2 downto 0):= 001; constant s1 :std_logic_vector(2 downto 0):= 010; constant s2 :std_logic_vector(2 downto 0):= 100;signal ss: std_logic_vector(2 downto 0);signal rdmemaddr,wrmemaddr: std_logic_vector(2 downto 0);signal rxdcnt: std_logic_vector(3 downto 0);signal rdmemdata, wrmemdata :std_logic_vector(7 downto 0);signal wrmem_s, wrrdy, dataclkout_s :std_logic;beginprocess(rst,clk)beginif rst = 0 thenwrmemdata 0);elsif clkevent and clk = 1 thenif den = 1 thenwrmemdata(7) = wrmemdata(6);wrmemdata(6) = wrmemdata(5);wrmemdata(5) = wrmemdata(4);wrmemdata(4) = wrmemdata(3);wrmemdata(3) = wrmemdata(2);wrmemdata(2) = wrmemdata(1);wrmemdata(1) = wrmemdata(0);wrmemdata(0) = rxd;end if;end if;end process;process(rst,clk)beginif rst = 0 thenrxdcnt 0);elsif clkevent and clk = 1 thenif den = 1 thenif rxdcnt = 9 thenrxdcnt = rxdcnt;elserxdcnt = rxdcnt +1;end if;elserxdcnt 0);end if;end if;end process;process(rst,clk)beginif rst = 0 thenss if wrrdy = 1 thenss = s1;elsif outen = 1 thenss ss ss ss = s0;end case;end if;end process;process(rst,clk)beginif rst = 0 thenwrrdy = 0;elsif clkevent and clk = 1 thenif ss = s1 thenwrrdy = 0;elseif rxdcnt = 8 thenwrrdy = 1;elsewrrdy = 0;end if;end if;end if;end process;wrmem_s = 0 when ss = s1 else 1;rdmem = 0 when ss = s2 else 1;csmem = 1 when ss = s1 or ss = s2 else 0;process(rst,clk)beginif rst = 0 thendataclkout_s = 0;elsif clkevent and clk = 1 thenif ss = s2 thendataclkout_s = 1;elsedataclkout_s = 0;end if;end if;end process;process(clk)beginif clkevent and clk = 1 thendataclkout = dataclkout_s;end if;end process;process(rst,clk)beginif rst = 0 thendataout 0);elsif clkevent and clk = 1 thenif ss = s2 thendataout = rdmemdata;end if;end if;end process;process(rst,clk)beginif rst = 0 thenwrmemaddr 0);elsif clkevent and clk = 1 thenif ss = s1 thenwrmemaddr = wrmemaddr +1;end if;end if;end process;process(rst,clk)beginif rst = 0 thenrdmemaddr 0);elsif clkevent and clk = 1 thenif ss = s2 thenrdmemaddr = rdmemaddr +1 ;end if;end if;end process;memaddr = wrmemaddr when wrmem_s = 0 else rdmemaddr;memdata = wrmemdata when wrmem_s = 0 else ZZZZZZZZ;rdmemdata = memdata;wrmem = wrmem_s;end behav;library IEEE;use IEEE.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity states isport (rst : in std_logic;clk : in std_logic;nscar: in std_logic;ewcar: in std_logic;nsred: out std_logic;nsgreen: out std_logic;nsyellow: out std_logic;ewred: out std_logic;ewgreen: out std_logic;ewyellow: out std_logic );end states;architecture behav of states is constant s0 :std_logic_vector(1 downto 0):= 00;- ewgreen constant s1 :std_logic_vector(1 downto 0):= 01; constant s2 :std_logic_vector(1 downto 0):= 11;- nsgreen constant s3 :std_logic_vector(1 downto 0):= 10;signal ss: std_logic_vector(1 downto 0);signal tm60s,tm40s :std_logic_vector(5 downto 0);signal tm3s :std_logic_vector(1 downto 0);signal entm60s,entm40s,entm3s,tm60soc,tm40soc,tm3soc :std_logic;beginprocess(rst,clk)beginif rst = 0 thenss if nscar = 1 thenif ewcar = 1 thenif tm60soc = 1 thenss = s1;end if;else ss if tm3soc = 1 thenss if nscar = 1 thenif ewcar = 1 thenif tm40soc = 1 thenss = s3;end if;end if;elsess if tm3soc = 1 thenss ss = s0;end case;end if;end process;process(rst,clk)beginif rst = 0 thenentm60s = 0;elsif clkevent and clk = 1 thenif ss = s0 thenentm60s = 1;elseentm60s = 0;end if;end if;end process;process(rst,clk)beginif rst = 0 thenentm40s = 0;elsif clkevent and clk = 1 thenif ss = s2 thenentm40s = 1;elseentm40s = 0;end if;end if;end process;process(rst,clk)beginif rst = 0 thenentm3s = 0;elsif clkevent and clk = 1 thenif ss = s1 or ss = s3 thenentm3s = 1;elseentm3s = 0;end if;end if;end process;process(rst,clk)beginif rst = 0 thentm60s = B000000;elsif clkevent and clk = 1 thenif entm60s = 1 thenif tm60s = 59 thentm60s = B000000;elsetm60s = tm60s + 1;end if;elsetm60s = B000000;end if;end if;end process;process(rst,clk)beginif rst = 0 thentm40s = B000000;elsif clkevent and clk = 1 thenif entm40s = 1 thenif tm40s = 39 thentm40s = B000000;elsetm40s = tm40s + 1;end if;elsetm40s = B000000;end if;end if;end process;process(rst,clk)beginif rst = 0 thentm3s = B00;elsif clkevent and clk = 1 thenif entm3s = 1 thenif tm3s = 2 thentm3s = B00;elsetm3s = tm3s + 1;end if;elsetm3s = B00;end if;end if;end process;process(rst,clk)beginif rst = 0 thentm60soc = 0; elsif clkevent and clk = 1 thenif tm60s = 59 thentm60soc = 1;elsetm60soc = 0;end if;end if;end process;process(rst,clk)beginif rst = 0 thentm40soc = 0; elsif clkevent and clk = 1 thenif tm40s = 39 thentm40soc = 1;elsetm40soc = 0;end if;end if;end process;process(rst,clk)beginif rst = 0 thentm3soc = 0; elsif clkevent and clk = 1 thenif tm3s = 2 thentm3soc = 1;elsetm3soc = 0;end if;end if;end process;process(rst,clk)beginif rst = 0 thennsred = 1;nsgreen = 0;nsyellow = 0;ewred = 0;ewgreen = 1;ewyellow nsred = 1;nsgreen = 0;nsyellow = 0;ewred = 0;ewgreen = 1;ewyellow nsred = 0;nsgreen = 0;nsyellow = 1;ewred = 0;ewgreen = 0;ewyellow nsred = 0;nsgreen = 1;nsyellow = 0;ewred = 1;ewgreen = 0;ewyellow nsred = 0;nsgreen = 0;nsyellow = 1;ewred = 0;ewgreen = 0;ewyellow end case;end if;end process;end behav;
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