第6章STM32F10x最小系统课件

,*,Click to edit Master text styles,Second Level,Third Level,Fourth Level,Fifth Level,Click to edit Master title style,Embedded System Development,嵌入式系统与应用,第,6,章,STM32F10 x,最小系统,6.1 STM32F10 x,系列微控制器简介,6.2,基于,Cortex-M3,的最小系统,6.3,存储器与总线架构,6.4 电源控制,6.5 复位,6.6 STM32,的时钟系统,6.7,仿真器与开发板,6.1 STM32,系列微控制器简介,STM32,系列是基于,ARM CortexM,核的,32,位闪存微控制器，集成度高、性能高、实时性、数字信号处理、低功耗、低电压操作的易开发的芯片，适合不同用户的需求。,片上存储器容量、集成外设、功能模块、封装形式等有所区别。,例：,STM32F10X,系列,STM32F10 x,系列产品编号,STM32F103,系列芯片,CORTEXM3 CPU72 MHz,6,kB,-64kB,SRAM,ARM Peripheral Bus,(max 72MHz),2,x,12-bit ADC16 channels/1Msps,1/2,x I,2,C,0/1,x SPI,1/2/4,x USART/LINSmartcard/IrDaModem Control,32/49/80*,I/Os,Up to 16 Ext.ITs,Flash I/F,32,kB-512kBFlash Memory,Temp Sensor,1,x USB 2.0FS,1,x bxCAN 2.0B,6,x 16-bit PWM Synchronized AC Timer,2,x Watchdog,2/3/5,x 16-bit Timer,External Memory Interface*,JTAG/SW Debug,XTAL oscillators32KHz+416MHz,Power SupplyReg 1.8VPOR/PDR/PVD,DMA 3 to 11*Channels,Nested vect IT Ctrl,2,x SPI/I2S*,2,x DAC*,1,x SDIO*,Image Sensor*,1,x USART/LINSmartcard/IrDaModem-Ctrl,1,x SPI,Bridge,Bridge,1,x Systic Timer,ARM Lite Hi-Speed BusMatrix/Arbiter(max 72MHz),Int.RC oscillators32KHz+8MHz,PLL,Clock Control,RTC/AWU,ARM Peripheral Bus,(max 36MHz),20,B Backup Regs,STM32F103,功能框图,第,6,章,STM32F10 x,最小系统,6.1 STM32F10 x,系列微控制器简介,6.2,基于,Cortex-M3,的最小系统,6.3,存储器与总线架构,6.4 电源控制,6.5 复位,6.6 STM32,的时钟系统,6.7,仿真器与开发板,6.2,基于,Cortex-M3,的最小系统,什么是最小系统,？,在,尽可能减少上层应用的情况下，能够使系统运行的最小化模块配置,。,“,最小系统,”,称,“,嵌入式,核心控制模块,”,更,贴切,一些,。,最小系统的组成：,电源、时钟、复位电路、存储系统、调试系统。,Cortex-M3,MPU,Flash,SRAM,Timer,Reset,JTAG,UART,Power,基于,Cortex-M3,的最小系统,时钟模块,通常经,ARM,内部锁相环进行相应的倍频，以提供系统各模块运行所需的时钟频率输入,复位模块,实现对系统的复位,电源系统：,调试系统：,JTAG/SW,模块,实现对程序代码的下载和调试,UART,模块,实现对调试信息的终端显示,存储系统：,Flash,存储模块,存放启动代码、操作系统和用户应用程序代码,SDRAM,模块,为系统运行提供动态存储空间，是系统代码运行的主要区域,基于,Cortex-M3,的,STM32F10 x,最小系统,第,6,章,STM32F10 x,最小系统,6.1 STM32F10 x,系列微控制器简介,6.2,基于,Cortex-M3,的最小系统,6.3,存储器与总线架构,6.4 电源控制,6.5 复位,6.6 STM32,的时钟系统,6.7,仿真器与开发板,6.3,存储器与总线架构,1,、总线架构,STM32,的各外围模块与,Cortex-M3,内核，通过各类总线连接在一起，形成一个有机的整体。,Cortex-M3,的,ICode,、,DCode,、,System,总线和,DMA,总线,四,个驱动单元，,与闪存存储器接口、,SRAM,和,AHB2APB,桥三个被动单元，,通过总线矩阵联接在一起,。,总线矩阵采取轮换算法仲裁、协调内核,System,总线和,DMA,主控总线之间的访问。,AHB,外设通过总线矩阵与系统总线相连，允许,DMA,访问。,两个,AHB/APB,桥在,AHB,和,2,个,APB,总线间提供同步连接。,APB1,操作速度限于,36MHz,，,APB2,操作于全速,72MHz,。,2,、存储器映像,STM32F1xx,Cortex-M3,有,32,根地址线，所以它的寻址空间大小为,232 bit=4GB,程序存储器、数据存储器、外设寄存器、输入输出端口被组织在同一,4GB,线性地址空间内。,把地址从,0 x4000 0000,至,0 x5FFF FFFF(512MB),的地址分配给片上外设。,外设存储器映像,STM32F103,外设寄存器组起始地址,起始地址,外设,总线,0 x4,0,02,2,400-,0 x4,0,02 3FFF,保留,AHB,0 x4,0,02,2,000-,0 x4,0,02,2,3,FF,闪,存接口,0 x4,0,02,1,400-,0 x4,0,02 1FFF,保留,0 x4,0,02,1,000-,0 x4,0,02,1,3,FF,复位和,时钟,0 x4,0,02,0,400-,0 x4,0,02 0FFF,保留,0 x4,0,02,0,000-,0 x4,0,02,0,3,FF,DMA,0,x,4,0,0,1,3C,0,0-,0,x,40,0,1,3,FFF,保留,APB2,0 x4,0,01,3,800-,0 x4,0,01 3BFF,USAR,T,1,0 x4,0,01,3,000-,0 x4,0,01,3,3,FF,SPI1,0 x4,0,01,2,C00-,0 x40,0,1 2FFF,TIM1,时钟,0 x4,0,01,2,800-,0 x4,0,01 2BFF,ADC2,0 x4,0,01,2,400-,0 x4,0,01,2,7,FF,ADC1,0 x4,0,01,1,800-,0 x4,0,01 1BFF,GPIO,端口,E,0 x4,0,01,1,400-,0 x4,0,01,1,7,FF,GPIO,端口,D,0 x4,0,01,1,000-,0 x4,0,01,1,3,FF,GPIO,端口,C,0,x,4,0,01,0,C00,-,0 x40,0,1 0FFF,GPIO,端口,B,0 x4,0,01,0,800-,0 x4,0,01 0BFF,GPIO,端口,A,0 x4,0,01,0,400-,0 x4,0,01,0,7,FF,E,X,T,I,0 x4,0,01,0,000-,0 x4,0,01,0,3,FF,AFIO,外设存储器映像,STM32F103,寄存器组起始地址,起始地址,外设,总线,0 x4,0,00,7,000-,0 x4,0,00,7,3,FF,电源控制,APB1,0 x4,0,00,6,C00-,0 x40,0,0 6FFF,后备寄存器,(BKP),0 x4,0,00,6,800-,0 x4,0,00 6BFF,保留,0 x4,0,00,6,400-,0 x4,0,00,6,7,FF,bxCAN,0 x4,0,00,6,000-,0 x4,0,00,6,3,FF,USB,的,SRAM,2,5,6,x,1,6,位,0 x4,0,00,5,C00-,0 x40,0,0 5FFF,USB,寄存器,0 x4,0,00,5,800-,0 x4,0,00 5BFF,I2C2,0 x4,0,00,5,400-,0 x4,0,00,5,7,FF,I2C1,0 x4,0,00,5,000-,0 x4,0,00 4FFF,保留,0 x4,0,00,4,800-,0 x4,0,00 4BFF,USAR,T,3,0 x4,0,00,4,400-,0 x4,0,00,4,7,FF,USAR,T,2,0 x4,0,00,3,800-,0 x4,0,00 3BFF,SPI2,0 x4,0,00,3,400-,0 x4,0,00,3,7,FF,保留,0 x4,0,00,3,000-,0 x4,0,00,3,3,FF,独立看门狗,(IWDG),0 x4,0,00,2,C00-,0 x40,0,0 2FFF,窗口看门,狗,(WWDG),0 x4,0,00,2,800-,0 x4,0,00 2BFF,R,T,C,0 x4,0,00,0,800-,0 x4,0,00 0BFF,TIM4,定时器,0 x4,0,00,0,400-,0 x4,0,00,0,7,FF,TIM3,定时器,0 x4,0,00,0,000-,0 x4,0,00,0,3,FF,TIM2,定时器,嵌入式闪存,Flash,存储器映像*,STM32F10 xxx Flash,高密度,闪存模块的组织,模块,名称,地址,大小,(,字节,),主存储块,页,0,0 x0800 0000-0 x0800 03FF,2K,页,1,0 x0800 0400-0 x0800 07FF,2K,页,255,0 x0807 F800-0 x0807 FFFF,2K,信息块,系统存储器,0 x1FFF F000-0 x1FFF F7FF,2K,用户选择字节,0 x1FFF F800-0 x1FFF F80F,16,闪存接口寄存器,FLASH_ACR,0 x4002 2000-0 x4002 2003,4,FALSH_KEYR,0 x4002 2004-0 x4002 2007,4,FLASH_OPTKEYR,0 x4002 2008-0 x4002 200B,4,FLASH_SR,0 x4002 200C-0 x4002 200F,4,FLASH_CR,0 x4002 2010-0 x4002 2013,4,FLASH_AR,0 x4002 2014-0 x4002 2017,4,保留,0 x4002 2018-0 x4002 201B,4,FLASH_OBR,0 x4002 201C-0 x4002 201F,4,FLASH_WRPR,0 x4002 2020-0 x4002 2023,4,擦写次数：,1000,次,4,、,STM32F10X,的,三种,启动模式,通过,BOOT1:0,引脚选择,不同,启动模式，实现实例：,启动模式选择管脚,启动模式,说明,BOOT1,BOOT0,X,0,从,用户闪存,(,片内,Flash,),启动,这是正常的工作模式,(,编好的程序已下载到,Flash),0,1,从,系统存储器,启动,芯片出厂时在这个区域预置了一段,Bootloader,1,1,从片内,SRAM,启动,这种模式可以用于调试,STM32F10X,的,三种,启动模式,通过选择管脚,设置,BOOT,配置，内置,Flash,、系统存储,区、内置,SRAM,会分别被,映射到地址,0 x00,(,启动存储区,),；,CPU,从的,0 x0000_0004,地址的值给,PC,，开始,执行代码,。,从,系统存储器,启动：厂