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Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,*,*,UMC Confidential, No Disclosure,Data Prepared by,Morris L.Yeh, umc.Fab-8AB.PEI.Logic-2,Page,55,Introduction on Fab flow and semiconductor industry,- for IT related employee,Morris L. Yeh,UMC.Fab8AB.PEI.Logic2,Outline,1.,Fab flow and Transistor working,2. IC manufacturing chain,3. Filed application,4. The Trend,The Roadmap,1.1,Transistor Working,1.,Whats the Transistor ?,2.,Whats the Transistor structure ?,3.,Hows the transistor working ?,4.,Transistor and System revolution,3.1 Hows the clock running in the transistor ring?,3.2 Hows the information broadcasting in a system ?,1.,Whats the Transistor ?,Transistor Working,In Digital application, the transistor play the role of switch in the system just like a mechanical switch , it means that the key component to storage the,0,and,1,State 1,State 0,But we deployed the Solid-State and Quantum physics to realize the solid-state switch - Transistor in silicon industry, its more size shrinkage, high speed, high performance and lower energy required than the prior arts.,State 1,State 0,2.,Whats the Transistor structure ?,Transistor Working,Gate Oxide,UMC.Fab8B. Generic 0.25um logic Ti-Salicide Process,Poly,TiSi,2,Spacer,Source,Drain,Channel Length,LDD,POLY,The transistor included 3 terminal which likes the switch : 1. Poly Gate play the role of control or input terminal, the Drain play the role of output terminal and the Source play the role of reference or ground.,3.,Hows the transistor working ?,Transistor Working,State 1,Drain Bias (charge),Times,Level (V),State 0,Gate Bias (discharge),Times,Level (V),State 1,Drain Bias (recharge),Times,Level (V),Voltage on the Drain terminal (output),=,In the Digital application, the transistor behaviors more likes a Capacitor :,1. Drain Bias ( Capacitor Charge ) : The charge storage on the Drain side.,2. Gate Bias ( Capacitor Discharge ) : The storage charge flow from Drain to Source,3. Drain Bias again ( Gate floating, Capacitor Recharge ) : The charge storage again.,3.1 Hows the clock running in the transistor ring?,The video shown the 49 stages,NOT,gate series which constructed the ring oscillator, In the left NOT gate diagram, if the input terminal become state 0, the PMOS was turn ON, and NMOS turned off, it means that the Vcc flow into Output terminal, the Output state become 1, and according quantum physics, the current flow the channel means that electron-hole pair recombination, and the light emission will be detected by the cooled infrared camera.,The Ring Oscillator was the tool to measure the system clock and speed.,GND,Vcc,Output,Input,PMOS,NMOS,NOT,Gate,State 0,On,Off,State 1,State 1,Off,On,State 0,3.2 Hows the information broadcasting in a system ?,Generally, theres a few people could understood the information broadcasting in a chip, especially on the system debug, the product engineer hard to detect the defect in system level. The liquid-nitrogen-cooled infrared Camera could detect the hot spot emission which generated by the electron-hole pair combination. The defect could be detected once the signal flow to the defect node, the system will be hold and hot spot frozen on the defect node.,FIG. 1. The first transistor. Brattain and Bardeens pnp point-contact germanium transistor operated as a speech amplifier with a power gain of 18 on December 23, 1947. (,Bell Labs, Lucent,),Gate Oxide,Poly,TiSi,2,Spacer,Source,Drain,Channel Length,FIG. 3. The worldwide smallest transistor Gate length 0.061 um. (,Bell Labs, Lucent,),FIG. 2. The UMC post generation 0.25um standard transistor (,UMC,),4.1,The Transistor revolution,The First Transistor,1947 Bell labs.,The UMC 0.25um Transistor,1999, UMC,The worldwide leadship,2001 Bell labs. Lucent,Device Integration and Technology drive,1.2,Fab flow,1.,Lithography concept and cycle,4.,Transistor Layer (Front-end) definition,5.,Routing Layer (Back-end) definition,3.,Module composition and integration,2.,Module definition,Lithography concept -,physical cycle,Photo Resist Coating,Mask & DUV Stepper Exposure,PHOTO,Photo Resist Development,PHOTO,Etching (Wet/Dry),Photo Resist Stripping,ETCH,Film Deposition,Raw material,Thin Film,ThinFilm-PHOTO-ETCH,Physical layer formation cycle,Fab Flow,Lithography concept -,Implant cycle,Photo Resist Coating,Mask & DUV Stepper Exposure,PHOTO,Photo Resist Development,PHOTO,Furnace film growth,Raw material,Diffusion,Ion Implant,Photo Resist Stripping,Diffusion,Diffusion-PHOTO- Diffusion,Implant layer cycle,Fab Flow,1.2,Fab flow,1.,Lithography concept and cycle,4.,Transistor Layer (Front-end) definition,5.,Routing Layer (Back-end) definition,3.,Module composition and integration,2.,Module definition,Photo:,Raw material :,Reticle, Photo Resist,Equipment :,I-Line(MUV), DUV, EUV,(Stepper, SCANNER),Vendors:,Nikon, ASML,2.,Module definition -,PHOTO,The PHOTO concept was general Optics lithography to reproduce the specific patterns. Today we deployed the UV Excimer laser for the light, According to Optics principle, generally the wavelength of the light should be less than one tenth of half pitch, so if the technology shrink, the Exposure light source should be pushed into deeply UV zone.,Thin-Film:,Raw material :,Metal Target, Chemical,Equipment :,Sputter, RTP, CVD (AP, PE, LP, SP, MO), Scubber,Vendors:,AMAT, Novellus, TEL, ASM.,2.,Module definition -,Thin Film,In general we can split the Thin-Film into two field, one is Physics dominated (PVD), the other is Chemical dominated (CVD),The PVD means that no chemical reaction assisted in the process, just simply accelerated Ar atom to bombard the target to evaporate the target and deposit on the wafer, such likes Sputter.,The CVD means that the chemical reaction on the wafer or chamber to deposit a film on the surface,CVD,PVD,Chemical reaction,Etch,Raw material :,Solvent, Reactive gas,Equipment :,Dry Etch (RIE), Wet Bench (Chemical Station),Vendors:,AMAT, Novellus, TEL, ASM.,2.,Module definition -,ETCH,In general we can call that RIE in the term of Dry etching, the dry etching which dominated by the Physical Ion bombard and chemical reaction with the surface to evaporated the byproducts.,Reactive ion bombard,Diffusion,Raw material :,Chemical Gas, Isotope gas,Equipment :,Implanter , Furnace,Vendors:,Eaton, Varian, KE, TEL.,2.,Module definition -,Diffusion,In the diffusion, therere two methods to deliver the dopant into the silicon wafer :,. Implant :,To accelerate the isotope and direct bombard the wafer to deliver the dopant into right depth with right concentration.,.,Furnace :,To use thermal diffusion potential to deliver the dopant into right depth with right concentration.,CM P,Raw material :,Slurry, polish pad,Equipment :,CMP (W-CMP, Oxide-CMP, Cu-CMP),Vendors:,AMAT, COBAT, Strasbaugh,2.,Module definition -,CMP,In general, the CMP like the polish arts, but deployed the chemical-mechanical assistant. Therere two factors dominated the CMP process:,. First,is chemical hydrolysis slurry to hydrolyze the surface,.Second,is the slurry abrasive to remove the hydrolyte which under the mechanical dominated.,1.2,Fab flow,1.,Lithography concept and cycle,4.,Transistor Layer (Front-end) definition,5.,Routing Layer (Back-end) definition,3.,Module integration,2.,Module definition,Process Flow,Layer (Route),Module(Step),3.,Module integration,1.2,Fab flow,1.,Lithography concept and cycle,4.,Transistor Layer (Front-end) definition,5.,Routing Layer (Back-end) definition,3.,Module composition and integration,2.,Module definition,Brief Process Flow - First Layer (Diffusion),P-sub,(Silicon wafer),SiN (Nitrid),Pad oxide,1.1. Wafer Start,1.2. PAD Oxidation,110A (stress buffer),1.7.,SiN (Nitrid) Deposition,1.5KA,1.8.,Diffusion Lithography :,1.8.1 P.R. coating,1.8.2 Stepper Exposure,1.8.3 Development,Photo Resistor coating,Diffusion mask,Stepper Exposure,Diffusion P.R.,P-sub,(Silicon wafer),SiN (Nitrid),Pad oxide,Diffusion P.R.,P-sub,(Silicon wafer),SiN (Nitrid),Pad oxide,STI,STI,Brief Process Flow - First Layer (Diffusion) cont,1.7. Trench (STI) Plasma Etching,1.7.1 SiN Etching,1.7.2 Silicon Etching,1.8. Photo Resistor remove,Brief Process Flow - First Layer (Diffusion) cont,1.7. APCVD STI refill,1.7.1 Liner Oxide Growth,1.7.2 APCVD Oxide deposition,1.7.3 STI Furnace 1000C Densify,1.8. STI CMP,1.9. SiN remove,Diffusion P.R.,P-sub,(Silicon wafer),SiN (Nitrid),Pad oxide,STI,STI,STI,N-WELL Mask,Brief Process Flow - Well formation,P.R. Coating,N-WELL P.R.,Stepper Exposure,2.1 N-WELL Formation :,2.1.1 N-WELL PR coating,2.1.2 N-WELL Lithography,2.1.3 Development,2.1.4 N-WELL implant,2.1.5 PR stripping,2.2 P-WELL Formation :,2.2.1 P-WELL PR coating,2.2.2 P-WELL Lithography,2.2.3 Development,2.2.4 P-WELL implant,2.2.5 PR stripping,P-sub(Silicon),Sac. oxide,STI,PWELL,N-WELL,P.R. Coating,P-WELL Mask,Stepper Exposure,N-WELL Implant,1. N-WELL- 1,2. N-WELL- 2,7. P MOS - VT,8. P MOS anti-punch,P-WELL Implant,1. P-WELL- 1,2. P-WELL- 2,7. N MOS - VT,8. N MOS anti-punch,Brief Process Flow - Gate Oxide and POLY,PR coating,P-sub (Silicon),NWELL,PWELL,Gate Oxide,TG Mask,Stepper Exposure,Gate Oxide 2,UPOLY growth,3 Gate Oxide Formation :,3.1 Thick Gate Oxide Growth,3.2 PR coating,3.3 TG Lithography,3.4 Development,3.5 RCA-A Wet etching,3.6 PR stripping,3.7 Thin Gate Oxide Growth,4. Poly Growth,4.1 undope. POLY growth,4.2 N+POLY PR coating,4.3 N+POLY Lithography,4.4 Development,4.5 N+POLY implant and PR Strip,PR Coating,N+POLY Mask,N+POLY PR,N+POLY implant,Stepper Exposure,Brief Process Flow - Gate Engineering,P-sub,NWELL,STI,PWELL,Poly,PR coating,Poly Mask,NLDD,N-LDD,N-PKT,N-LDD,N-PKT,P-LDD PR,P-LDD,P-PKT,Stepper Exposure,N-LDD Implant,P-LDD implant,5 Poly Gate Formation :,5.1 Poly annealing,5.2 PR coating,5.3 POLY Lithography,5.4 Development,5.5 POLY Gate etching,5.6 PR stripping,5.7 Thin Oxide Growth,6. LDD (Light Dope Drain) implant,6.1 N-LDD Lithography,(ellipsis),6.2 NLDD / N-PKT implant,6.3 P-LDD Lithography,(ellipsis),6.4 PLDD / P-PKT implant,Brief Process Flow - Drain Engineering,P-sub,NWELL,STI,PWELL,Poly,PR coating,Poly Mask,NLDD,N-LDD,N-PKT,N-LDD,N-PKT,P-LDD PR,P-LDD,P-PKT,N+ PR,N+,N+,P+ PR,P+,P+ Implant,N+ implant,Gate Oxide,UMC.Fab8B. Generic 0.25um logic Ti-Salicide Process,Poly,TiSi,2,Spacer,Source,Drain,Channel Length,7 Poly Gate Formation :,7.1 Poly annealing,7.2 PR coating,7.3 POLY Lithography,7.4 Development,7.5 POLY Gate etching,7.6 PR stripping,7.7 Thin Oxide Growth,8. LDD (Light Dope Drain) implant,8.1 N-LDD Lithography,(ellipsis),8.2 NLDD / N-PKT implant,8.3 P-LDD Lithography,(ellipsis),8.4 PLDD / P-PKT implant,1.2,Fab flow,1.,Lithography concept and cycle,4.,Transistor Layer (Front-end) definition,5.,Routing Layer (Back-end) definition,3.,Module composition and integration,2.,Module definition,Brief Process Flow - ILD Passivation,P-sub,NWELL,STI,PWELL,Poly,PR coating,Poly Mask,NLDD,N-LDD,N-PKT,N-LDD,N-PKT,P-LDD PR,P-LDD,P-PKT,N+ PR,N+,N+,P+ PR,P+,SAB,PSG,USG,9. Salicide Formation :,9.1 PETEOS-500A Cap Oxide dep.,9.2 SAB (Salicide-Block) Lithography,(ellipsis),9.3 Ti/Co sputtering,9.4 Salicidation RTP C49 annealing,9.5 Salicidation RTP C54 annealing,9.6 Ti residual Semi-tool wet clean,10. ILD Passivation,10.1 SiN 300A deposition,(Moisture and sodium block),10.2 AP-USG deposition,(Gap filling and B,P trap),10.3 TEOS-BPSG-14K deposition,(re-flow and planarization),10.4 ILD CMP,P-sub,NWELL,STI,PWELL,Poly,PR coating,Poly Mask,NLDD,N-LDD,N-PKT,N-LDD,N-PKT,P-LDD PR,P-LDD,P-PKT,N+ PR,N+,N+,P+ PR,P+,SAB,PSG,USG,PR Coating,Brief Process Flow - Contact Plug,Contact Mask,PR coating,Contact PR,Metal 1,DUV Stepper Exposure,11. Contact Plug Formation :,11.1 Contact Lithography,11.2 Contact Plasma Etching,11.3 PR strip,11.4 Barrier layer deposition,(Ti + TiN for well contact),11.5 RTP annealing,11.6 Glue Layer deposition,(Ti + TiN for plug adhesion),11.5 WCVD filling,11.6 WCMP,11.7 Metal Liner deposition,(Ti + TiN for Metal adhesion),11.8 Metal Sputter,Brief Process Flow - Backend routine,(Aluminum line),P-sub,NWELL,STI,PWELL,Poly,PR coating,Poly Mask,NLDD,N-LDD,N-PKT,N-LDD,N-PKT,P-LDD PR,P-LDD,P-PKT,N+ PR,N+,N+,P+ PR,P+,SAB,PSG,USG,PR Coating,Contact Mask,PR coating,Contact PR,Metal 1,Contact plug,PR Coating,Metal 1 mask,Metal 1 PR,Metal 1,HDP-1,PEOX,Cap Oxide,PR Coating,MVIA1 mask,MVIA1 PR,Metal 2,Stepper Exposure,Stepper Exposure,12. IMD deposition,12.1 HDP-Oxide deposition,( Gap filling),12.2 PE-Oxide Deposition,( Planarization and uniformity),12.3 IMD CMP,12.4 Cap PE-Oxide,13. MVIA plug formation,13.1 MVIA Lithography cycle,13.2 MVIA Etching and PR strip,13.3 Glue Layer deposition,(Ti + TiN for plug adhesion),13.4 WCVD filling,13.5 WCMP,13.6 Metal Liner deposition,(Ti + TiN for Metal adhesion),13.7 Metal Sputter,Brief Process Flow - Aluminum line,MVIA1,MVIA2,MVIA3,MVIA4,MVIA5,Passivation,M5-8K,M6-8K,M4-5K,M3-5K,M2-5K,M1-5K,UMC.Fab8B. Generic 0.25um logic Ti-Salicide Process,P-sub,NWELL,STI,PWELL,Poly,PR coating,Poly Mask,NLDD,N-LDD,N-PKT,N-LDD,N-PKT,P-LDD PR,P-LDD,P-PKT,N+ PR,N+,N+,P+ PR,P+,SAB,PSG,USG,Contact plug,Brief Process Flow - Backend routine,(Copper Dual Damascene),PR Coating,Metal 1 mask,Metal 1,Metal 2 Mask,Stepper Exposure 2,MVIA1 Mask,Metal 2,Stepper Exposure 1,Stepper Exposure 3,14. ILD/M1 Damascene,14.1 PEOX-3.6K deposition,14.2 M1 Lithography,14.3 M1 Trench Etching,14.4 M1 Cu Electroplate (ECP),14.5 Cu CMP,15. M2/ MVIA1 Dual Damascene,15.1 PEOX-9K deposition,15.2 M2 Lithography,15.3 M2 Trench Etching,15.4 MVIA1 Lithography,15.5 MVIA1 Plug Etching,15.6 Trench Liner deposition,15.7 M2/MVIA1 Cu ECP,15.8 Cu CMP,Brief Process Flow - Copper Dual Damascene,Complexity,Advantage The higher conductivity of copper simplifies interconnect routing. This reduces the number of interconnect levels from 12 to 6, which removes upwards of 200 process steps and has a direct impact on device yield.,Power Advantage,Chips with copper interconnect will operate with approximately 30% less power at a given frequency than chips with aluminum interconnect. This technology will enable devices with significantly higher performance for mobile applications.,Cost Advantage,The semiconductor industry has historically reduced the cost per function by 25% to 30% per year. The reduction in critical process steps with the dual-Damascene copper process reduces the overall cost by 30% per interconnect level.,Speed Advantage,At 0.13 m, the interconnect delay for copper and low-k materials is approximately one-half that of aluminum and SiO2. Copper is a clear choice at 0.13 m and smaller because it provides speed enhancement with no sacrifice of device reliability.,Why Copper ?,Diffusion barrier,SiN,IMD -Via,low k Ox,Trench,Etching Stop,SiN,IMD- Trench,Low k Ox,Hard Mask,SiN,ARC,Lithography,SiON,Trench first,Via last,Etching,Cu Barrier,TaN,Cu seed CVD,Cu ECP,Cu CMP,Brief Process Flow - Copper Dual Damascene,Outline,1.,Fab flow and Transistor working,2. IC manufacturing chain,3. Filed application,4. The Trend,wafer processing,Front-end,Lot/wafer,Back-end,wafer Sorting,( C/P testing),C/P : Circuit probing,Wafer/dice,System,Design,Synthesis, simulation, and physical layout Design,Mask Tooling,Designing stage,Reticle,.gds dB,System,2. IC manufacturing chain - Front-end,IDM,Fabless,Turnkey,Fundry,Die sawing,Wire bond,Solder bumped,Package,Final Test,Burn-in,Back-end,Wafer/dice,Dice/chip,chip,chip,chip,Field Application,module,2. IC manufacturing chain - Backend,Assembly and Testing,IDM,System House,IC Design flow,Simulation and Testbility design Level,Design Verification,Physical layout generation ,design optimization,Test pattern generation Level,Tape out , DRC, Mask Tooling and Fab Pilot Level,System Design Entry and Analysis,System Synthesis and,Technology Optimization,Level,Backend Assembly flow,Wafer level,Die level,Chip level,IC manufacturing chain - Capital, cycle and gross margin,Design,Production,Time To Market = 0.5 0.75 year (without qualification),Outline,1.,Fab flow and Transistor working,2. IC manufacturing chain,3. Filed application,4. The Trend,3. Filed application,Outline,1.,Fab flow and Transistor working,2. IC manufacturing chain,3. Filed application,4. The Trend,Device Integration and Technology drive,Notes:(1)Box Center represents start at Pilot Production Schedule.,(2)Based on logic and eSRAM roadmap.,(3)SIA = Semiconductor Industry Association,UMC / SIA Technology Road Map,1999,2000,2001,2002,0.18,m,0.15,m,Cu,0.18,m,0.13,m,Cu,2003,2004,SIA,0.10,m,Cu,0.07,m,Cu,0.18,m,0.13,m,Cu,0.10,m,Cu,UMC,Technology Road Map,Note: (1) Box Center represents Pilot Production Schedule begins.,1998,1999,2000,2001,eDRAM,0.35,m,0.25,m,0.18,m,Logic,eSRAM,Mixed-Mode/RF,0.15,m,0.25,m,0.18,m,Embedded Flash Memory,0.35,m,0.25,m,0.13,m,0.18,m,Cu,0.15,m,0.25,m,0.18,m,0.13,m,Cu,0.18,m,Hardware and process limitation,The two major limitations : one is Gate high k dielectric material , the other is Gate line width limitation, it means that beyond DUV light source should be developed, and the cooperating should be developed which contained Reticle, Photo Resist, Stepper, Inspection and Metrology tools.,Generation and Application mix,*,Based on Current Demand/Forecast Projections,UMC technology mix,ASET product mix,Therere two significant trend in these two figures :,The technology will be driven into deep sub-micron technology, and the PC didnt dominate the the field application mix.,Morgan Stanley,: Semi growth follows GDP movement, and my shadow: Semi growth follows GDP movement,Upward or Downward ?,演讲完毕，谢谢观看！,内容总结,Introduction on Fab flow and semiconductor industry。UMC.Fab8AB.PEI.Logic2。I-Line(MUV), DUV, EUV。AMAT, COBAT, Strasbaugh。1.8.1 P.R. coating。Diffusion P.R.。P.R. Coating。N-WELL P.R.。2.2.2 P-WELL Lithography。2.2.4 P-WELL implant。(re-flow and planarization)。14. ILD/M1 Damascene。( C/P testing)。
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