IC工艺集成简介课件

IC,工艺集成简介,IC工艺集成简介,什么是,IC FAB,的产品？,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,后道,back end,(After CT),前道,Front end,(Before and,including CT),什么是IC FAB的产品？+ + + + +,Process flow,CMOS Front End,active area,channel doping,gate electrode,source/drain extensions,spacers,Junctions,LOCSAL,Salicide,AL BEOL process flow,PMD module,contact module,Al metal 1 module,IMD 1 module,via 1 module,Al metal 2 module,via 2 module,Al metal 3 module,passivation module,Process flowCMOS Front End AL,Process flow,CMOS Front End,active area,channel doping,gate electrode,source/drain extensions,spacers,Junctions,LOCSAL,Salicide,AL BEOL process flow,PMD module,contact module,Al metal 1 module,IMD 1 module,via 1 module,Al metal 2 module,via 2 module,Al metal 3 module,passivation module,Process flowCMOS Front End AL,CMOS,的基本结构,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,N+,N+,P-,Gate(Metal),Source,Drain,CMOS的基本结构+ + + + + +,Process flow,CMOS Front End,active area,channel doping,gate electrode,source/drain extensions,spacers,Junctions,LOCSAL,Salicide,AL BEOL process flow,PMD module,contact module,Al metal 1 module,IMD 1 module,via 1 module,Al metal 2 module,via 2 module,Al metal 3 module,passivation module,Process flowCMOS Front End AL,CMOS,的基本结构,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,CMOS的基本结构+ + + + + +,Isolation,（隔离）,A.Why do we need Isolation,B.Basic LOCOS process,C.Birds beak effect,D.Shallow Trench Isolation,Isolation（隔离） A.Why do we n,Why do we need isolation?,So the purpose of isolation is:,Electrical isolation between adjacent devices,Definition of the active area region of the transistor,P-Well,N-Well,p,+,P,+,P,+,N,+,N,+,P Channel,N Channel,Parasitic P Channel,Parasitic N Channel,Why do we need isolation?So t,Methods of Isolation,Conventional:Local Oxidation of Silicon(LOCOS),New: Shallow Trench Isolation(STI),Methods of Isolation Conventi,BASIC LOCOS PROCESS(1),Pad oxide,Si3N4,Pad oxide-Thermal oxidation,CVD Si3N4 Mask,Photo,Etching,Strip,场氧,BASIC LOCOS PROCESS(1)Pad oxid,BASIC LOCOS PROCESS(2),Field oxidation,（,LOCOS,）：,3000 4000A,900C-1000C, 48h, wet O2,P-Well,N-Well,p,+,场氧,Etching Si3N4/SiO2,BASIC LOCOS PROCESS(2) Field,IC工艺集成简介课件,IC工艺集成简介课件,LOCOS,s limitation,LOCOS is appropriate for CMOS down to around 1 um,Limiting factors:,birds beak formation,nitride lifting,Birds beak dimensions can be reduced by:,increasing nitride thickness,decreasing pad oxide thickness,BUT,this increases mechanical stress and can create defects in silicon,New technique required for sub 0.18um CMOS,Shallow Trench Isolation (STI),LOCOSs limitationLOCOS is app,Shallow Trench Isolation(STI),Dry etch a shallow trench,CVD SiO2,Etch back SiO2,Advantage : no BB effectmeet 0.35um process,good planarization,Shallow Trench Isolation(STI),Process flow,CMOS Front End,active area,channel doping,gate electrode,source/drain extensions,spacers,Junctions,LOCSAL,Salicide,AL BEOL process flow,PMD module,contact module,Al metal 1 module,IMD 1 module,via 1 module,Al metal 2 module,via 2 module,Al metal 3 module,passivation module,Process flowCMOS Front End AL,CMOS,的基本结构,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,CMOS的基本结构+ + + + + +,阱,WELL,介绍,阱的形成,单阱双阱技术,工艺,阱 WELL 介绍,Well (Tube),为什么要用：可以在衬底上同时制造,N/PMOS,掺杂类型,Doping type,B,+,-P-well,P,+,-N-well,Well (Tube)为什么要用：可以在衬底上同时制造N/P,P-WELL,N-WELL,sub,P-WELL N-WELLsub,形成,在,P/N,衬底上掺杂,B+/P+,注入,/,扩散适当的深度,掺杂范围：,2,8*10,12,/cm,2,注入能量,100,250kev +thermal drive-in,形成在P/N衬底上掺杂B+/P+,N-well,掩蔽,层,:,氧化硅, 400A,光刻,N-well,：开出,N,阱,N-well,注入,: P, 250keV, 0.9E13 atoms/cm2,阱,推进（退火）,Substrate,+ + + + + +,P,+,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,退火：使杂质均匀分布，同时除去（减少）由注入引起的缺陷,至此形成均匀的双阱结构,N-well掩蔽层:氧化硅 400A 光刻N-well：,光刻,P-well,：,开出,P,阱,P-well,注入:,B, 180keV, 8.5E12 atoms/cm2,推进,B,+,P-Well,N-Well,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,光刻P-well：开出P阱P-well 注入: B, 1,Single well & Twin well,技术,Single well, n well in p substrate or p well in n substrate,n-well,P+,P+,n+,p substrate,+,+,+,+,+,Transistor in well had lowered mobility due to high level of well counter doping,Simpler process,Single well & Twin well 技术Sing,Single well & Twin well,技术,Double well(“Twin tub”),-Lightly doped p-substrate,Form both n and p well,n-well,P+,P+,n+,p substrate,n+,p-well,Allows well profiles to be,separately optimized for each transistor,Single well & Twin well 技术Doub,工艺,1.Thermal Drive-in,离子注入,+,长时间高温退火（,drive-in,）,P-sub,P,+,Epi,B,+,注入能量低,-,表面浓度最高,ADVANTAGES,：,不需要高能离子注入机，成本低,DISADVANTAGES,：,离子横向扩散导致,well,尺寸增大,-,芯片尺寸增大,表面注入浓度大,沟道中电子,/,空穴迁移率下降,性能下降,工艺1.Thermal Drive-inP-subP+Epi,2,.,High Energy Implant (Retrograde well),高能离子注入无需,drive-in,P-sub,P,+,Epi,B,+,Retrograde well,Peak well doping below surface,ADVANTAGES:,减小横向扩散，,Well,尺寸小,表面注入浓度小,沟道中电子,/,空穴迁移率大,性能好,DISADVANTAGES:,需要高能离子注入，成本高,2.High Energy Implant (Retrog,Process flow,CMOS Front End,active area,channel doping,gate electrode,source/drain extensions,spacers,Junctions,LOCSAL,Salicide,AL BEOL process flow,PMD module,contact module,Al metal 1 module,IMD 1 module,via 1 module,Al metal 2 module,via 2 module,Al metal 3 module,passivation module,Process flowCMOS Front End AL,CMOS,的基本结构,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,CMOS的基本结构+ + + + + +,gate module(1),purpose,growth gate oxide,define gate electrodes,gate module(1)purpose,gate module(2),gate module(2),Process flow,CMOS Front End,active area,channel doping,gate electrode,source/drain extensions,spacers,Junctions,LOCSAL,Salicide,AL BEOL process flow,PMD module,contact module,Al metal 1 module,IMD 1 module,via 1 module,Al metal 2 module,via 2 module,Al metal 3 module,passivation module,Process flowCMOS Front End AL,CMOS,的基本结构,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N-Well,P-Well,场氧,n,+,n,+,P,p,+,CMOS的基本结构+ + + + + +,source/drain extensions,purpose,limit hot carrier degradation,optimize drive current/transistor performance,how,control maximum electrical field in channel region,optimization of 2-dimensional doping profile which compromises between,short channel effects, series resistance, leakage current, drive current .,source/drain extensionspurpose,source/drain extensions,（,2,）,source/drain extensions（2）,Process flow,CMOS Front End,active area,channel doping,gate electrode,source/drain extensions,spacers,Junctions,LOCSAL,Salicide,AL BEOL process flow,PMD module,contact module,Al metal 1 module,IMD 1 module,via 1 module,Al metal 2 module,via 2 module,Al metal 3 module,passivation module,Process flowCMOS Front End AL,CMOS,的基本结构,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,CMOS的基本结构+ + + + + +,spacer module(1),purpose,realize offset for highly doped junctions,avoid bridging of silicide between gate electrode and junctions,spacer module(1)purpose,spacer module(2),spacer module(2),Process flow,CMOS Front End,active area,channel doping,gate electrode,source/drain extensions,spacers,Junctions,LOCSAL,Salicide,AL BEOL process flow,PMD module,contact module,Al metal 1 module,IMD 1 module,via 1 module,Al metal 2 module,via 2 module,Al metal 3 module,passivation module,Process flowCMOS Front End AL,CMOS,的基本结构,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,CMOS的基本结构+ + + + + +,junction module,（,1,）,purpose,realize source and drain regions for transistor,doping polysilicon gate electrodes : n-type for NMOS, p-type for PMOS,junction module（1）purpose,junction module,（,2,）,junction module（2）,Process flow,CMOS Front End,active area,channel doping,gate electrode,source/drain extensions,spacers,Junctions,LOCSAL,Salicide,AL BEOL process flow,PMD module,contact module,Al metal 1 module,IMD 1 module,via 1 module,Al metal 2 module,via 2 module,Al metal 3 module,passivation module,Process flowCMOS Front End AL,salicide module,purpose,reduce resistance poly lines and source/drain regions,salicide modulepurpose,IC工艺集成简介课件,Process flow,CMOS Front End,active area,channel doping,gate electrode,source/drain extensions,spacers,Junctions,LOCSAL,Salicide,AL BEOL process flow,PMD module,contact module,Al metal 1 module,IMD 1 module,via 1 module,Al metal 2 module,via 2 module,Al metal 3 module,passivation module,Process flowCMOS Front End AL,CMOS,基本结构,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,后道,（,back end),前道,（,front end),CMOS 基本结构+ + + + + +,后道的基本组成,后道的基本组成,IC工艺集成简介课件,IC工艺集成简介课件,Process flow,CMOS Front End,active area,channel doping,gate electrode,source/drain extensions,spacers,Junctions,LOCSAL,Salicide,AL BEOL process flow,PMD module,contact module,Al metal 1 module,IMD 1 module,via 1 module,Al metal 2 module,via 2 module,Al metal 3 module,passivation module,Process flowCMOS Front End AL,CMOS,基本结构,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,后道,（,back end),前道,（,front end),CMOS 基本结构+ + + + + +,PMD module,PMD module,Process flow,CMOS Front End,active area,channel doping,gate electrode,source/drain extensions,spacers,Junctions,LOCSAL,Salicide,AL BEOL process flow,PMD module,contact module,Al metal 1 module,IMD 1 module,via 1 module,Al metal 2 module,via 2 module,Al metal 3 module,passivation module,Process flowCMOS Front End AL,CMOS,基本结构,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,后道,（,back end),前道,（,front end),CMOS 基本结构+ + + + + +,Contact module,Contact module,Process flow,CMOS Front End,active area,channel doping,gate electrode,source/drain extensions,spacers,Junctions,LOCSAL,Salicide,AL BEOL process flow,PMD module,contact module,Al metal 1 module,IMD 1 module,via 1 module,Al metal 2 module,via 2 module,Al metal 3 module,passivation module,Process flowCMOS Front End AL,CMOS,基本结构,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,后道,（,back end),前道,（,front end),CMOS 基本结构+ + + + + +,Contact module,Contact module,Process flow,CMOS Front End,active area,channel doping,gate electrode,source/drain extensions,spacers,Junctions,LOCSAL,Salicide,AL BEOL process flow,PMD module,contact module,Al metal 1 module,IMD 1 module,via 1 module,Al metal 2 module,via 2 module,Al metal 3 module,passivation module,Process flowCMOS Front End AL,CMOS,基本结构,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,后道,（,back end),前道,（,front end),CMOS 基本结构+ + + + + +,IMD module (1),IMD module (1),IMD MODULE (2),IMD MODULE (2),Process flow,CMOS Front End,active area,channel doping,gate electrode,source/drain extensions,spacers,Junctions,LOCSAL,Salicide,AL BEOL process flow,PMD module,contact module,Al metal 1 module,IMD 1 module,via 1 module,Al metal 2 module,via 2 module,Al metal 3 module,passivation module,Process flowCMOS Front End AL,CMOS,基本结构,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,后道,（,back end),前道,（,front end),CMOS 基本结构+ + + + + +,VIA1 MODULE (1),VIA1 MODULE (1),VIA1 MODULE (2),VIA1 MODULE (2),VIA1 MODULE (3),VIA1 MODULE (3),VIA1 MODULE (4),VIA1 MODULE (4),Finally,.,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,后道,（,back end),前道,（,front end),Finally.+ + + +,IC工艺集成简介课件,衬底,P,型,硅片,材料检验,原始材料,: P,型,Si(100),15-25,.,cm.,激光标号,(Laser Mark),：在晶片边缘刻上批号,RCA,清洗：,RC1,：去有机杂质和颗粒,RC2,：去金属杂质,衬底,P型硅片材料检验,2024/9/2,75,P,+,+ + + + + +,+ + + + + +,N-well,掩蔽,层,:,氧化硅, 400A,光刻,N-well,：开出,N,阱,N-well,注入,: P, 250keV, 0.9E13 atoms/cm2,去胶,2023/9/975P+ + + + +,2024/9/2,76,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,B,+,光刻,P-well,：,开出,P,阱,P-well,注入:,B, 180keV, 8.5E12 atoms/cm2,去胶,2023/9/976+ + + + +,2024/9/2,77,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,阱,推进（退火）:,X,jn-well,=2.9,m,退火：使杂质均匀分布，同时除去（减少）由注入引起的缺陷,至此形成均匀的双阱结构,N-Well,P-Well,2023/9/977+ + + + +,2024/9/2,78,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + + +,BF2,光刻场区：,开出场区,P-,阱区场氧注入：,BF2,，,80keV,，,4E13,场氧注入：提高寄生场管的开启电压，防止寄生三极管的导通,N-Well,P-Well,去胶,2023/9/978+ + + + +,2024/9/2,79,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + + +,基氧 200,A,基氧用来缓解,Si3N4,与硅衬底之间的应力,漂光,SiO,2,沉积,Si3N4,（,1500A,）,Si3N4,层被用作为有源区在场氧化时的掩蔽层,光刻有源区,(Diffusion),：将场区窗口开出,刻蚀有源区：氮化硅,+,氧化硅刻蚀,去胶,N-Well,P-Well,2023/9/979+ + + + +,2024/9/2,80,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + + +,场氧化（,LOCOS,）：,3000 4000A,腐蚀,Si3N4/SiO2,N-Well,P-Well,场氧,N-Well,P-Well,2023/9/980+ + + + +,2024/9/2,81,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + + +,NMOS,防穿通及阈值电压调整注入：,预氧化：,200A,光刻,VTDV,Vtn,注入,: B,11,10kev ,1.2E+12/cm,2,.,VTDV,注入,: NMOS,防穿通注入,; B,11, 50KeV, 1.0E+12 /cm,2,.,Vtn,注入,:,调制阈值电压,防穿通注入,：,以防止有源区源漏之间相互穿通。,N-Well,P-Well,场氧,去胶,2023/9/981+ + + + +,2024/9/2,82,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + + +,PMOS,防穿通及阈值电压调整注入：,光刻,VTNH;,VTNH,注入,:PMOS,防穿通注入,As,150kev 2. 0E+11/cm,2,Vtp,注入,As,35 keV,5.0E+11/cm,2,去胶,N-Well,P-Well,场氧,2023/9/982+ + + + +,2024/9/2,83,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,预栅氧化清洗,(pre-gate clean): RCA+,稀释的,HF,酸清洗,目的是得到清洁而完整的单晶硅表面，这对确保栅氧层的高质量非常重要。,场氧,N-Well,P-Well,2023/9/983+ + + + +,2024/9/2,84,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,场氧,栅氧化硅,:,70A 3.3V; 110A 5V,有干氧和湿氧之分,N-Well,P-Well,2023/9/984+ + + + +,2024/9/2,85,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,多晶淀积,(,原位掺杂,),：,3000A,Pre-clean using HF vapor,WSi,x,淀积：,1250A,减少多晶条上的接触电阻,(Polycide),多晶光刻,刻蚀多晶,场氧,N-Well,P-Well,2023/9/985+ + + + +,2024/9/2,86,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,去胶,场氧,N-Well,P-Well,2023/9/986+ + + + +,2024/9/2,87,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,多晶氧化,:100A,（或者沉积一层薄的,TEOS,膜）,多晶氧化：修复因多晶刻蚀而造成的多晶边缘栅氧的,损伤，同时保护多晶条,场氧,N-Well,P-Well,2023/9/987+ + + + +,2024/9/2,88,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,As,N,管,LDD:,(,减缓热载流子效应,(Hot Carrier Effect),NLDD,光刻,NLDD,注入,As, 25kev,3E13 /cm,2,WSi,x,退火,:,RTP, 1000C, 10”,N-Well,P-Well,场氧,2023/9/988+ + + + +,2024/9/2,89,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,BF2,P,管,LDD,光刻,PLDD,PLDD,注入,BF2, 10keV, 1.3E13,/cm,2,N-Well,P-Well,场氧,2023/9/989+ + + + +,2024/9/2,90,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,边墙形成,TEOS,淀积：,T=2000A,TEOS,增密（退火）,边墙刻蚀,边墙用来隔离源（漏）与栅极,N-Well,P-Well,场氧,2023/9/990+ + + + +,2024/9/2,91,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,N,管源漏区,光刻,N+,区,N+,注入,As,3E+15 /cm,2,N-Well,P-Well,场氧,n,+,n,+,2023/9/991+ + + + +,2024/9/2,92,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,P,管源漏区,光刻,P+,区,区注入,BF2 20keV, 2E+15/cm,2,源漏退火,RTP:1020C, 10”,源漏结深,X,JN+,=0.18,m ,X,JP+,=0.18,m,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,2023/9/992+ + + + +,2024/9/2,93,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,金属前绝缘介质层（,PMD,）,淀积,SiON:,LPCVD, 800C,25-35nm,淀积,TEOS:,CVD,720C,100 nm.,淀积,BPSG,APCVD 1000nm B 3.6%;P4.0%,BPSG,增密,RTP,700C 30 min,化学机械抛光,CMP-PMD,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,2023/9/993+ + + + +,2024/9/2,94,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,淀积氧化硅,USG,APCVD,：,400nm,接触孔光刻,接触孔刻蚀,:,去胶,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,2023/9/994+ + + + +,2024/9/2,95,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,接触孔阻挡层淀积,Ti/TiN: 25 nm,.,TiN,可以阻止,W,与周围介质,(Si),之间的反应和元素扩散，同时可增强钨与介质之间的黏着力，但电阻率太高。,Ti,用来降低电阻率。,W-CVD,淀积,:,300 nm.,W-,返腐蚀,(Etch-back),（或者,W-CMP,）,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,2023/9/995+ + + + +,2024/9/2,96,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,金属夹层淀积：,Ti/Al(Cu)/Ti/TiN,Al(Cu) : 5500A.,TiN,：电阻率较高。顶层,TiN,作为光刻的,ARC(,抗反射层）。,Ti,和,TiN,还可阻止金属与介质之间的元素扩散。,Al(CuSi),：铝中掺少量铜或硅可以增强铝线的抗电迁移性能。,Ti/TiN,Ti,Al(Cu),N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,2023/9/996+ + + + +,2024/9/2,97,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,金属,1,光刻,金属,1,刻蚀,去胶,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,2023/9/997+ + + + +,2024/9/2,98,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,金属,1-2,间介质淀积及平坦化,氧化层淀积,1500 nm, HDP , 400,C; 750nm ,PECVD,400,C,.,化学机械抛光,N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,2023/9/998+ + + + +,2024/9/2,99,+ + + + + +,+ + + + + +,+ + + + + +,+ + + + + +,通孔,1,光刻,通孔,1,刻蚀,通孔阻挡层淀积,Ti/TiN: 25 nm.,W-CVD,淀积,:,600 nm.,W-,返腐蚀,(Etch-back),N-Well,P-Well,场氧,n,+,n,+,p,+,p,+,2023/9/999+ + + + +,2024/9/2,100,+ + + + + +,+