第二章CMOS制备基本流程

Click To Edit Title Style, , , , , ,*,2.1,CMOS,制造工艺流程简介,We,will,describe,a,modern,CMOS,process,flow.,Process,described,here,requires,16,masks and,100,process,steps.,1,第二,章,CMOS,制备基本流程,Stages of IC Fabrication,2,In,the,simplest,CMOS,technologies,we,need,to,realize simply,NMOS,and,PMOS,transistors,for circuits,like,those,illustrated,below.,CMOS,Digital,Gates,反相电路,或非门：同时输入低电平时才能获得高电平输出,3,PMOS,and,NMOS,wafer,cross section,after fabrication,2-Level,Metal,CMOS,两层互连布线的,CMOS,4,有源器件（,MOS,、,BJT,等类似器件），必须在外加,适当的偏置电压,情况下，器件才能正常工作。,对于,MOS,管，有源区分为源区和漏区，在进行互联之前，两者没有差别。,Choosing,a,Substrate,Active,Region,N,and,P,Well,Gate,Tip,or,Extension,Source,and,Drain,Contact,and,Local,Interconnect,Multilevel,Metalization,Processing,Phases,5,1,m Photoresist,40,nm SiO,2,Choose,the,substrate (type,orientation, resistivity,wafer,size),Initial,processing:,-,Wafer,cleaning,-,thermal,oxidation,H,2,O,(,40,nm,15,min.,900C),-,nitride,LPCVD,(,低压化学气相沉积,),(,80,nm ,800C),Substrate,selection:,-,moderately,high,resistivity (25-50,ohm-cm),-,(100),orientation,-,P-,type.,80,nm Si,3,N,4,Choosing,a,Substrate,Si,(100), P Type,2550,cm,1st,Mask,Photoresist,spinning,and,baking ,1,00C (,0.5,-,1.0,m),6,2.2,有源区的形成,Photolithography,-,Mask,#1,pattern,alignment and,UV,exposure,-,Rinse,away,non-pattern,PR,-,Dry,etch,the,Nitride,layer,-,Plasma,etch,with,Fluorine,CF,4,or,NF,4,Plasma,-,Strip,Photoresist (H,2,SO,4,或,O,2,plasma),Active,Area,Definition (,主动区,),SiO,2,Si,3,N,4,Photoresist,7,Wet,Oxide,(thick,SiO,2,),-,H,2,O,(,500,nm,90,min.,1000C),Strip,Nitride,layer,-,Phosophoric,acid (,磷酸,),or plasma,etch,，选择性问题,Field,Oxide,Growth,-,LOCOS:,Local,Oxidation,of Silicon (,局部硅氧化工艺,),SiO,2,Si,3,N,4,薄的,SiO,2,层，厚的,Si,3,N,4,层，避免鸟喙,(birds beak),的影响,8,场区,:,很厚的氧化层，位于芯片上不做晶体管、电极接触的区域，可以起到隔离晶体管的作用。,Photolithography (,套刻,),-,Mask,#2,pattern,alignment and,UV,exposure,Ion Implantation,离子注入,-,B+,ion,bombardment,Penetrate,thin,SiO,2,and,field SiO,2,-,反型,：半导体,表面,的少数载流子浓度等于体内的多数载流子浓度时，半导体表面开始反型。,-,150-200,k,eV,for,10,13,cm,-2,-,Implantation,Energy,and total,dose,adjusted,for depth,and,concentration,P-well,Fabrication,Strip,Photoresist,-,Rinse,away,non-pattern,PR,2.3 N,阱和,P,阱的形成,SiO,2,Photoresist,9,Ion,Implantation,-,P+,ion,bombardment,-,Penetrate,thin,SiO,2,and,field,SiO,2,-,300-400,k,eV,for,10,13,cm,-2,-,Implantation,Energy,and,total,dose,adjusted,for,depth,and,concentration,Strip,Photoresist,N-well,Fabrication,Photolithography,-,Mask,#3,pattern,alignment and,UV,exposure,-,Rinse,away,non-pattern,PR,10,Thermal Anneal (,热退火,),-,Repair,crystal,lattice,structure damage,due,to,implantation,Dry,Furnace,(N,2,ambient,，防止氧化层生成,),-,Anneal 30,min,800C,or RTA(,快速热退火,),10,sec,1000C,-,Drive-in 4-6,hours,1000,C,-,1100,C,Thermal,Anneal,and,Diffusion,N and P Drive-in (,扩散推进,),-,Thermal,diffusion,of,dopant,to shallower,than,desired,depth,-,Drive-in,is,a,cumulative process!,11,Photolithography,-,Mask,#4,pattern,alignment and,UV,exposure,-,Rinse,away,non-pattern,PR,-,B+,ion,bombardment,-,50-75keV,for,1-5,10,12,cm,-2,-,Implantation,Energy,and,total,dose,adjusted,for,depth,and,concentration,Strip,Photoresist,Threshold,Adjustment,P-type,NMOS,Ion,Implantation,2.4,栅电极的制备,开启电压调整,12,调整之前,P,阱的掺杂浓度,调整时的注入剂量,Threshold,Adjustment,N-type,PMOS,Photolithography,-,Mask,#5,pattern,alignment and,UV,exposure,-,Rinse,away,non-pattern,PR,-,As+,ion,bombardment,-,75-100keV,for,1-5,10,12,cm,-2,-,Implantation,Energy,and,total,dose,adjusted,for,depth,and,concentration,Strip,Photoresist,Ion,Implantation,13,Remove,existing,gate,region oxide,Furnace,Steps,-,Thermal,Anneal,-,Oxide,growth,3-5,nm,-,O,2,ambient,- 0.5-1 hour 800C,Gate,Oxide,Growth,栅极氧化层生长,-,HF,etch,，具有良好的选择性,- Dry,Furnace,(N,2,ambient),- 30,min,800C,14,LPCVD,Deposition,of,Si,-,Silane,硅烷,Amorphous,or,polycrystalline,silicon,layer,results,Ion,Implantation,-,P,+,or,As,+,(N,+,),implant,dopes,the,poly (typically,5,10,15,cm,-2,),Polysilicon,Gate,Deposition,0.3-0.5,um,SiO,2,多晶硅薄膜,15,热分解,Photolithography,-,Mask,#6,pattern,alignment and,UV,exposure,Plasma,Etch,-,Anisotropic,etch,各向异性蚀刻,-,Vertical,etch,rate,high,-,Lateral,etch,rate,low,Gate,Patterning,（,栅极的图形化,）,-,Rinse,away,non-pattern,PR,Clorine,(,氯,),or,Bromine (,溴,),based,for SiO,2,selectivity,16,目标：,NMOS,器件中的,N,-,注入区,PMOS,器件中的,P,-,注入区,多晶硅栅的两侧形成侧壁隔离层的薄氧,化层,2.5,前端或延伸区,(LDD),的形成,17,LDD:,Lightly,Doped,Drain (,轻掺杂漏,),Reduce,short,channel,effects,due,to,gate,voltage magnitudes,and,electric,fields,Source,and,Drain,must,be,layered,as,NMOS:N+ N- P,or,PMOS:,P+ P- N,Extension,(LDD),Formation,NMOS,Photolithography,-,Mask,#7,pattern,alignment and,UV,exposure,-,Rinse,away,non-pattern,PR,-,P,+,ion,bombardment,-,50keV,for,5,10,13,cm,-2,Strip,Photoresist,Ion,Implantation,18,Photolithography,Mask,#8,pattern,alignment,and,UV,exposure,Rinse,away,non-pattern,PR,Ion,Implantation,B,+,ion,bombardment,50,k,eV,for,5,10,13,cm,-2,Strip,Photoresist,Extension,(LDD),Formation,PMOS,19,SiO,2,隔离介质层,CVD or LPCVD Deposition of SiO,2, Silane and Oxygen,Or,0.5 um, Provides spacing between gate and source-drain.,SiO,2,Spacer Deposition,20,Photolithography,Mask,#6,oversized,pattern,alignment,and,UV,exposure,Rinse,away,non-pattern,PR,Vertical,etch,rate,high,Lateral,etch,rate,low,Strip,Photoresist,Anisotropic,Spacer,Etch,Plasma,Etch,Anisotropic,etch,Flourine,based,21,Screen,Oxide,Growth,Thin,SiO,2,layer,10,nm,to scatter,the,implanted,ions,Photolithography,Mask,#9,pattern,alignment,and,UV,exposure,Rinse,away,non-pattern,PR,Ion,Implantation,As+,ion,bombardment,75,keV,for,2-4,10,15,cm,-2,Strip,Photoresist,NMOS,Source,and,Drain,Implant,2.6,源漏区的形成,Arsenic,Reduce,channeling,22,Photolithography,Mask,#10,pattern,alignment,and,UV,exposure,Rinse,away,non-pattern,PR,Ion,Implantation,B+,ion,bombardment,5-10,keV,for,1-3,10,15,cm,-2,Strip,Photoresist,PMOS,Source,and,Drain,Implant,23,N,+,and,P,+,Drive-in,Thermal,diffusion,of,dopant,to shallower,than,desired,depth,Drive-in,is,a,cumulative process!,Dry,Furnace,(N,2,ambient),Anneal 30,min,900C,or RTA,60,sec,1000,C,-,1050,C,Transient,Enhanced,Diffusion,(TED,瞬态增强扩散,),Higher,than,normal,diffusivity,due,to crystal,damage,Thermal,Annealing, Thermal Anneal, Repair crystal lattice structure damage due to implantation,24,2.7,接触与局部互联的形成,Contacts,and,Interconnects, Titanium sputtering local contacts, Conformal Coat with SiO,2, Planarization, Tungsten Plug vias, Aluminum Metal Deposition, Repeat, Coat, Planarize, Plug, Metal deposition,25,HF,etch,to,remove,thin,SiO,2,Remove,screen,oxide,from drain,source,and,ploy,gate regions,Dip (,浸,),for,a,few,seconds with HF,Contact,Openings,LDD and Sidewall structure, NMOS: Lateral N+ N- P N- N+, PMOS: Lateral P+ P- N P- P+,26,Titanium,Deposition,Ti,is,deposited,by sputtering (typically,100,nm).,Ti,target,hit,with Ar,+,ions,in,a vacuum,chamber,The,Ti,is,reacted,in,an N,2,ambient,Forms,TiSi,2,and,TiN (typically,1,min,600,-700,C).,TiSi,2,has,excellent contact,characteristics (,良好的导体,),TiN,does,not,but,can be,used,for,local,wiring (,导电材料，短程互连布线,),TiSi,2,TiN,27, Photolithography, Mask #11 pattern alignment,and,UV,exposure,Rinse,away,non-pattern,PR,TiN,etch,NH,4,OH:H,2,O,2,:H,2,O (1:1:5),Strip,Photoresist,Local,TiN,Interconnect,Thermal Treat in Ar,减小电阻, 1 min 800 C,28,用,TiN,作为局部互连引线,Conformal,layer,of SiO,2,is,deposited,by CVD,or,LPCVD (typically,1,m),P,SG,(,磷硅玻璃,),or,B,PSG (,硼,磷硅玻璃,),磷：,Surface,passivation (,表面钝化,),硼：,Glass,reflow,for partial planarization (,加热，令表面平整,),Chemical,Mechanical Polishing,(CMP,化学机械抛光,), Planarize,the,wafer surface,平坦化, Polish,with,high,pH silica slurry (,硅酸盐研磨浆料,),Conformal,Coat,and,Planarize,2.8,多层金属互连的形成,SiO,2,29,表面不平坦带来很多问题,两种解决方法：,Photolithography,Mask,#12,pattern,alignment and,UV,exposure,Rinse,away,non-pattern,PR,SiO,2,plasma,etch,Anisotropic,etch,Strip,Photoresist,Vias,to,1st,Metal,30,选择第一层金属布线需要与下层器件结构形成连接的接触孔位置,接触孔形成,Via,Deposition,Tungsten,Plugs (,插头,),TiN,or,Ti/TiN,barrier,layer,粘结层,/,阻挡层，增强金属与,SiO,2,的粘附性,Sputtering,or,CVD (few,tens,of,nm),CVD,Tungsten,(W), Chemical,Mechanical Polishing,(CMP),Planarize,the,wafer surface,Polish,with,high,pH silica,slurry,31,Etch,Contact,Holes,(,接触孔的蚀刻,),or,Line,Trenches (,沟道,),Fill,etched,regions (,蚀刻区的填充,),Planarize (,平坦化,),CMP,process,Also,removes,material,that,“overflowed,holes,or,trenches”,Damascene,Process,大马士革镶嵌工艺,32,大马士革镶嵌工艺包括：,Strip,Photoresist,Metal,#1,Deposition,第一层金属布线,Photolithography, Mask #13 pattern alignment and UV exposure, Rinse away non-pattern PR, Anisotropic plasma etch,33,SiO,2,Al,光刻胶, Sputtered Aluminum, Al with small amounts of,Si,and,Cu,- Cu reduces electromigration,避免电迁移现象带来的断路,-,Si,降低接触电阻,Multiple,Metal,Layers, Deposits Oxide Layer, CMP, Photolithography Mask #14, Etch Vias, Deposit via material, CMP, Deposit Next Metal Layer, Photolithography Mask #15, Final passivation layer of Si,3,N,4,is deposited by PECVD and patterned with Mask #16.,防止,Na+,、,K+,污染和封装中的机械损伤, Final anneal and alloy in,forming gas (10% H,2,in N,2,), 30min 400-450 C,形成良好的欧姆接触，降低,Si/SiO,2,界面的电荷,34,SiO,2,W,TiN,Si,3,N,4,或,SiO,2,Intel,processor,chip,52MB,SRAM,chips,on,a,12”,wafer,Photos,of,state-of-the-art,CMOS,chips,(from,Intel,website).,90,nm,technology.,35,Summary,of,Key,ideas,This chapter serves as an introduction to CMOS technology.,It provides a perspective on how individual technologies like oxidation and ion implantation are actually used.,There are many variations on CMOS process flows used in industry.,The process described here is intended to be representative, although it is simplified compared to many current process flows.,Perhaps the most important point is that while individual process steps like oxidation and ion implantation are usually studied as isolated technologies, their actual use is complicated by the fact that IC manufacturing consists of many sequential steps, each of which must integrate together to make the whole process flow work in manufacturing.,36,作业：,MEMS,器件制备,最早的,MEMS,执行器之一：静电驱动的微马达,37,