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Chap1.Fundamentals.1Fundamentals on Testing and Design for TestabilityChap1.Fundamentals.2Design Verification,Testing and DiagnosisDesign Verification:Ascertain the design perform its specified behaviorTesting:Exercise the system and analyze the response to ascertain whether it behaves correctlyDiagnosis:To locate the cause of misbehavior after the incorrect behavior is detectedChap1.Fundamentals.3Some Real Defects in ChipsProcessing Faultsmissing contact windowsparasitic transistorsoxide breakdownMaterial Defectsbulk defects(cracks,crystal imperfections)surface impurities(ion migration)Time-Dependent Failuresdielectric breakdownelectromigrationPackaging Failurescontact degradationseal leaksChap1.Fundamentals.4Faults,Errors and FailuresFault:A physical defect within a circuit or a system May or may not cause a system failureError:Manifestation of a fault that results in incorrect circuit(system)outputs or states Caused by faultsFailure:Deviation of a circuit or system from its specified behavior Fails to do what it should do Caused by an errorFault-Error-Failure Chap1.Fundamentals.5Scenario for Manufacture TestTEST VECTORSMANUFACTUREDCIRCUITCOMPARATORCIRCUIT RESPONSEPASS/FAILCORRECTRESPONSESChap1.Fundamentals.6Purpose of Manufacture TestingVerify Manufacture of CircuitImprove System ReliabilityDiminish System CostCost of repair goes up by an order of magnitude each step away from fab line0.5550500ICTestBoardTestSystemTestWarrantyRepair1011001000Costperfault(Dollars)B.Davis,The Economics of Automatic Testing,McGRAW-HILL,1982.Chap1.Fundamentals.7Testing and QualityASICFabricationTestingYield:Fraction ofgood partsRejectsShipped PartsQuality:Defective partsper million(DPM)*Quality of shipped part is a function ofyield Y and the test (fault)coverage T.Chap1.Fundamentals.8Fault Coverage*Fault coverage T is the measure of theability of a set of tests to detect a givenclass of faults that may occur on thedevice under test.T=#of detected faults#of possible faultsChap1.Fundamentals.9Defect Level*Defect Level,DL is the fraction of theshipped parts that are defective.DL=1-Y(1-T)Y:yieldT:fault coverageChap1.Fundamentals.10Relating Defect Level to Fault Coverage01020304050607080901000.1.2.3.4.5.6.7.8.91Y=.99Y=.90Y=.75Y=.50Y=.25Y=.10Y=.01Y=YieldFault Coverage,T(%)DL=1-Y(1-T)Chap1.Fundamentals.11Defect Level,Yield and Fault Coverage50%90%67,00075%90%28,00090%90%10,00095%90%5,00099%90%1,00090%90%10,00090%95%5,00090%99%1,00090%99.9%100Yield Fault Coverage DPMChap1.Fundamentals.12ASICWhat is ASIC:Application Specific Integrated CircuitsWhy we need ASICsMicroelectronic economicsVolumeTime to marketQualityChap1.Fundamentals.13ASICs Demand*While ASIC density and complexity haveexploded,global market pressures haveincreased the demand for both QualityQualityand Quick TurnaroundQuick Turnaround.Chap1.Fundamentals.14Test Development Time vs.TestabilityControllability and observability as a percentage of circuit coveredMeasured development timesExtrapolated curve403530252015105020406080100Chap1.Fundamentals.15Time-to-Market ModelLost revenuedue to delayTimeGrowthStagnationDeclineDelay in reaching market*1/81/8 delay of the productlifetime reduces 1/31/3 revenue.Chap1.Fundamentals.16Why Testing is Difficult?Test application time can be exploded for exhaustive testing of VLSIFor a combinational circuit with 50 inputs,we need 250=1.126x1015 test patterns.Assume one test per 10-7sec,it takes 1.125x108sec=3.57yrs.to test such a circuit.Test generation of sequential circuits are even more difficult.Lack of Controllability and Observability ofFlip-Flops(Latches)Functional testing may not be able to detect the physical faults Chap1.Fundamentals.17How To Do TestFault Modeling Identify target faultsLimit the scope of test generationMake analysis possibleTest GenerationAutomatical or ManualFault SimulationAssess completeness of testsTestability AnalysisAnalyze a circuit for potential problem on test generationDesign For TestabilityDesign a circuit for guaranteed test generationIntroduce both area overhead and performance degradationChap1.Fundamentals.18The New Challenges for VLSI TestingChip,Board,Module&System for highPerformanceDensityIntegrationReliabilityChap1.Fundamentals.19Reference:Digital Systems testing and testable design ISBN：0716781794 Author：Breuer mELVIN a.etcVLSI Testing digital and mixed analogure/digital techinques ISBN：085296 901 5 Author：Stanley LhurstChap1.Fundamentals.20DEC Alpha Chip(1994)*64-bit RISC*200 MHz*400 MIPS*200 Mflops*16.8*13.9-mm die*1.68 million Txs*431-pin package*3.3-V*30W power consumption.Chap1.Fundamentals.21Multi-Chip Module(MCM)*IBM Enterprise System/9000*Type 9121Model 320*Air-Cooled Processor Technology*Integration of bipolar chips,CMOS SRAMchips,and ECL&DCS logic circuitry in a TCM(thermal conduction module)(Ref:IBM J.RES.DEVELOP.,May 1991)Chap1.Fundamentals.22Wafer Scale Integration(WSI)*ELSA(European Large SIMD Array),a wafer-scale two-dimensional arrayof single-bit processors*MUSE(Matrix Update Systolic Experiment),MIT Lincoln LaboratoryChap1.Fundamentals.23Traditional Design FlowConduct testing after designDesignSpec.DesignToo LargeorToo Slow?Testability AnalysisTestabilityImprovement?DoneDesignforTestabilityNoYesNoYesChap1.Fundamentals.24The Infamous Design/Test Wall30 years of experience proves thattest after design does not work!Functionally correct!Were done!Oh no!What doesthis chip do?!Design EngineeringTest EngineeringChap1.Fundamentals.25New Design MissionDesign circuit to optimally satisfy or trade-off their design constraints in terms of area,performance and testability.PERFORMANCEAREATESTABILITYChap1.Fundamentals.26New VLSI Design FlowStructureLogicSynthesisFunction/BehaviorDesignSpec.NoSatisfied?CircuitSynthesisPlacement/RoutingATPGMASKTESTSYesTestabilityAnalysisTestableDesignRulesTestplanChap1.Fundamentals.27Why Model Faults?I/O function tests inadequate for manufacturingFunctionality ponent&interconnection testingExhaustive testing is Prohibitively expensiveChap1.Fundamentals.28Why Model Faults?Fault model identifies target faultsModel faults most likely to occur Fault model limits the scope of test generationCreat tests only for the modeled faultsFault model makes effectiveness measurable by experimentsFault coverage can be computed for specific test patterns to reflect its effectivenessFault model makes analysis possible Associate specific defects with specific test patternsChap1.Fundamentals.29Fault ModelingModeling the effects of physical defectson the logic function and timing.Physical Defects:Silicon Defects Photolithographic Defects Mask Contamination Process Variations Defective OxideChap1.Fundamentals.30Fault Modeling(contd)Electrical Effects:Shorts(Bridging Faults)Opens Transistor Stuck-On/Open Resistive Shorts and Opens Change in Threshold Voltages Logic Effects:Logic Stuck-At-0/1 Slower Transition(Delay Faults)AND-Bridging,OR-BridgingChap1.Fundamentals.31Fault Modeling*Stuck-At Faults*Bridging Faults*Transistor Stuck-On/Open Faults*IDDQ Faults*Functional Faults*Memory Faults*PLA Faults*Delay Faults*State Transition FaultsChap1.Fundamentals.32Single Stuck-At Faults011101/01/0stuck-at-0True ResponseTest VectorFaulty ResponseAssumptions:Only one line is faulty.Faulty line permanently set to 0 or 1.Fault can be at an input or output of a gate.Chap1.Fundamentals.33Multiple Stuck-At FaultsSeveral stuck-at faults occur at the same time Important in high density circuitsFor a circuit with k linesthere are 2k single stuck-at faultsthere are 3k-1 multiple stuck-at faults Chap1.Fundamentals.34Why Single Stuck-At Fault Model?*Complexity is greatly reduced.Many different physical defects may be modeled by the same logicalsingle stuck-at fault.*Single stuck-at fault is technology independent.Can be applied to TTL,ECL,CMOS,etc.*Single stuck-at fault is design style independent.Gate Arrays,Standard Cell,Custom VLSI*Even when single stuck-at fault does not accuratelymodel physical defects,the tests derived for logicfaults are still valid for these defects.*Single stuck-at tests cover a large percentage ofmultiple stuck-at faults.Chap1.Fundamentals.35Multiple FaultsMultiple Stuck-fault coverage by single-fault tests of combinational circuit:4-bit ALU(Hughes&McCluskey,ITC-84)All double and most triple-faults covered.Large circuits(Jacob&Biswas,ITC-87)Almost 100%multiple faults covered for circuits with 3 or more outputs.No results available for sequential circuits.Chap1.Fundamentals.36Bridging FaultsABfgABfgABfgABfgTwo or more normally distinct points(lines)are shorted togetherLogic effect depends on technologyWired-AND for TTLWired-OR for ECLCMOS?Chap1.Fundamentals.37CMOS Transistor Stuck-ON0stuck-on?IDDQ*Transistor stuck-on may causeambiguous logic level.*When input is low,both P and Ntransistors are conducting causingincreased quiescent current,calledIDDQ fault.depends on the relative impedances of the pull-up&pull-down networksChap1.Fundamentals.38CMOS Transistor Stuck-OPEN0stuck-open?=previous state*Transistor stuck-open may causeoutput floating.Chap1.Fundamentals.39CMOS Transistor Stuck-OPEN(contd)0 1stuck-open1 0/0 0InitializationvectormemorybehaviourCan turn the circuit into a sequential oneStuck-open faults require two-vector testsChap1.Fundamentals.40Fault Coverage in a CMOS Chip020406080100100020003000Test Vectorsstuck and open faultsstuck faults onlyChap1.Fundamentals.41Summary of Stuck-Open Faults*First report:Wadsack,Bell Syst.Tech.J.,1978*Recent results:Woodhall,et al,ITC-87Experiment with 1-micron CMOS chips:4552 chips passed parametric test 1255 chips(27.57%)failed tests for stuck-at faults 44 chips(0.97%)failed tests for stuck-open faults 4 chips with stuck-open faults passed tests for stuck-at faultsConclusion Stuck-at faults are about 29 times more frequent than stuck-open faults About 91%of chips with stuck-open faults may also have stuck-at faults Faulty chips escaping tests for stuck-at faults=0.121%Chap1.Fundamentals.42Functional Faults*Fault effects modeled at a higher levelthan logic for function modules,such asDecodersMultiplexersAddersCountersRAMsROMsChap1.Fundamentals.43Functional Faults of Decoderf(Li/Lj):Instead of line Li,Line Lj is selectedf(Li/Li+Lj):In addition to Li,Lj is selectedf(Li/0):None of the lines are selected2-bitDecoderABABABABABChap1.Fundamentals.44Memory FaultsParametric FaultsOutput LevelsPower ConsumptionNoise MarginData Retention TimeFunctional FaultsStuck Faults in Address Register,Data Register,and Address DecoderCell Stuck FaultsAdjacent Cell Coupling FaultsPattern-Sensitive FaultsChap1.Fundamentals.45Memory FaultsPattern-sensitive faults:the presence of a faulty signal depends on the signal values of the nearby pointsMost common in DRAMsAdjacent cell coupling faultsPattern sensitivity between a pair of cells0 0 00 d b0 a 0a=b=0=d=0a=b=1=d=1Chap1.Fundamentals.46Memory Testing*Test sequences can be derived withoutmuch difficulty for each specific fault.However,the length of the testsequence can be prohibitive.e.g.A pattern sensitive test is 5n2 longfor an n-bit RAM.Testing a 1-M bit chip at 10 ns perpattern would take 14 hours.For a 64-M bit chip it would take 6 years.Chap1.Fundamentals.47PLA Faults*Stuck Faults*Crosspoint FaultsExtra/Missing Transistors*Bridging Faults*Break FaultsChap1.Fundamentals.48Stuck Faults in PLAABCf1f2P1P2ABCf1f2P1P2AND-ArrayOR-Array*S-A-0&S-A-1 on inputs,inputinvertors,product lines,and outputs*Easy to simulate in gate modelGate-level representationChap1.Fundamentals.49Missing Crosspoint Faults in PLAABCf1f2ABCf1f2GrowthDisappearances-a-1s-a-0*Missing crosspoint in AND-array-Growth fault*Missing crosspoint in OR-array-Disappearance faultEquivalent stuck fault representationChap1.Fundamentals.50Extra Crosspoint Faults in PLA*Extra crosspoint in AND-array-Shrinkage or disappearance fault*Extra crosspoint in OR-array-Appearance faultEquivalent stuck fault representationABCf1f2ABCf1f2Disapp.1Shrinkage0AppearanceChap1.Fundamentals.51Bridging Faults in PLA*Shorting of adjacent lines(layoutdependent)*Faulty value identical on shorted lines*Faulty value AND/OR function ofshorted signals*A large number of bridging faults mapinto stuck or crosspoint faultsChap1.Fundamentals.52Summary of PLA Faults*Crosspoint Faults-80 85%covered by stuck-fault tests-Layout-dependence in folded PLA*Bridging Faults-99%covered by stuck-fault tests-Layout-dependence in all PLA(Ref:Agrawal&Johnson,ICCD-86)Chap1.Fundamentals.53Why Delay Testing?*There are defects on the chip which allowsit to pass the DC stuck-fault testing,butcauses it to fail when operated at systemspeed.A chip may pass testing under 1MHz operation but not under 10 MHzChap1.Fundamentals.54Gate-Delay-FaultSlow to rise,slow to fallx is slow to rise when channel resistance R1 is abnormally highVDDVDDCLXXL-HR1Rp:channel resistanceChap1.Fundamentals.55Gate-Delay-Fault*Disadvantage:Delay faults resulting from the sumof several small incremental delaydefects may not be detected.slowChap1.Fundamentals.56Path-Delay-Fault Propagation delay of the path exceedsthe clock interval.The number of paths grows exponentiallywith the number of gates.Chap1.Fundamentals.57State Transition Graph*Each state transition is associated with 4 tuple:(source state,input,output,destination state)S2S3S1I2/O2I1/O1Chap1.Fundamentals.58Single State Transition Fault ModelS2S3S1I/OI/O*A fault causes a single state transitionto a wrong destination state.Chap1.Fundamentals.59Single State Transition Fault Model*Has M(N-1)faults for a M-transition N-statemachine*Is modeled in the state transition level andindependent of implementation*Is dominated by most physical faults for allpossible implementation(contd)Chap1.Fundamentals.60Transition Faults in State Graph*Any irredundant physical faults will causesome changes in the state graph.Single or multiple transitions will be corrupted.A transition is corrupted if its:(a)Output label is changed,or(b)Destination state is changed,or(c)Both(a)and(b).A test to type(b)fault will detect type(a)and(c)faults.Chap1.Fundamentals.61Test for a State Transition Fault*A test sequence for a fault causing a type(b)corruption on a transition consists of threesubsequences:(1)Initialization sequence(2)Input label of the faulty transition(3)State-pair differentiating sequence between good and faulty statesCSS1S2S3SnS2S3SnI1/O1I/OI/OI1/O1(1)(2)(3)Chap1.Fundamentals.62Test for a State Transition Fault(contd)*Subsequences(1)and(2)alreadyproduce faulty output responses if theoutput label of the target transition iscorrupted.*Only need to generate tests for the statetransition faults causing wrongdestination states.Chap1.Fundamentals.63Multiple-State-Transition(MST)Faults*A test sequence that detects allMST faults detects all irredundantphysical fault.*A machine of M transitions and Nstates has:NM-1 MST faultsM(N-1)SST faultsChap1.Fundamentals.64Why Logical Fault ModelingFault analysis on logic rather than physical problemComplexity is reducedTechnology independentSame fault model is applicable to many technologiesTesting and diagnosis methods remain valid despite changes in technologyTests derived may be used for physical faults whose effect on circuit behavior is not completely understood or too complex to be analyzedStuck-at fault:The most popular logical fault modelChap1.Fundamentals.65Fault DetectionA test(vector)t detects a fault f ifft detects f ExamplexX1X2X3Z1Z2s-a-1Z1=X1X2Z2=X2X3Z1f=X1Z2f=X2X3z t()*zft()=1The test 100 detects f because z1(100)=0 while z1f(100)=1Chap1.Fundamentals.66Sensitization z(1011)=0 zf(1011)=11011 detects the fault f (G2 stuck-at 1)v/vf:v =signal value in the fault free circuit vf=signal value in the faulty circuitX1X2X3X4G1G2G3G410111s-a-10/110/10/1zChap1.Fundamentals.67SensitizationA test t that detects a fault fActivates f (or generate a fault effect)by creating different v and vf values at the site of the faultPropagates the error to a primary output w by making all the lines along at least one path between the fault site and w have different v and vf valuesA line whose value in the test changes in the presence of the fault f is said to be sensitized to the fault f by the test A path composed of sensitized lines is called a sensitized pathChap1.Fundamentals.68DetectabilityA fault f is said to be detectable if there exists a test t that detects f;otherwise,f is an undetectable faultFor an undetectable fault fNo test can simultaneously activate f and create a sensitized path to a primary outputzfx()=z x()Chap1.Fundamentals.69Undetectable FaultG1 output stuck-at-0 fault is undetectableUndetectable faults do not change the function of the circuitThe related circuit can be deleted to simplify the circuit xs-a-0abczG1Chap1.Fundamentals.70Test SetComplete detection test set:A set of tests that detect any detectable faults in a class of faultsThe quality of a test set is measured by fault coverageFault coverage:Fraction of faults that are detected by a test setThe fault coverage can be determined by fault simulation95%is typically required for single stuck-at fault model99.9%in IBM Chap1.Fundamentals.71Typical Test Generation FlowSelecttarget faultGenerate testfor targetFault simulateDiscarddetected faultsNo more faultsDoneChap1.Fundamentals.72Fault EquivalenceA test t distinguishes between faults a and b if Two faults,a&b are said to be equivalent in a circuit,iff the function under a is equal to the function under b for any input combination(sequence)of the circuit.for all tNo test can distinguish between a and bAny test which detects one of them detects all of themChap1.Fundamentals.73Fault EquivalenceAND gate:all s-a-0 faults are equivalentOR gate:all s-a-1 faults are equivalentNAND gate:all the input s-a-0 faults and the output s-a-1 faults are equivalentNOR gate:all input s-a-1 faults and the output s-a-0 faults are equivalentInverter:input s-a-1 and output s-a-0 are equivalent input s-a-0 and output s-a-1 are equivalentChap1.Fundamentals.74Equivalence Fault Collapsingn+2 instead of 2n+2 faults need to be considered for n-input gatess-a-1s-a-1s-a-1s-a-1s-a-1s-a-1s-a-1s-a-1s-a-0s-a-0s-a-0s-a-0s-a-0s-a-0s-a-0s-a-0Chap1.Fundamentals.75Equivalencein a Wire*B-sa0 and B-sa1 need not to beconsidered.AB*Fault equivalence:A sao B saoA sa1 B sa1Chap1.Fundamentals.76Fault EquivalenceTwo equivalent faults are detected by exactly the same teststhree faults shown are equivalents-a-1s-a-0s-a-1xxxChap1.Fundamentals.77Fault DominanceA fault b is said to dominate another fault a in an irredundant circuit,iff every test(sequence)for a is also a test(sequence)for b.No need to consider fault b for fault detectionChap1.Fundamentals.78Fault DominanceAND gate:Output s-a-1 dominates any input s-a-1NAND gate:Output s-a-0 dominates any input s-a-1OR gate:Output s-a-0 dominates any input s-a-0NOR gate:Output s-a-1 dominates any input s-a-0Dominance fault collapsing:The reduction of the set of faults to be analyzed based on dominance relationChap1.Fundamentals.79Fault DominanceDetect A sa1:Detect C sa1:C sa1 -A sa1Similarly C sa1 -B sa1 C sa0 -A sa0 C sa0 -B sa0z t()zft()=CDCE()DCE()=DCD=1 C=0,D=1()z t()zft()=CDCE()DE()=1 C=0,D=1()or C=0,E=1()ABCDExxxChap1.Fundamentals.80Equivalence&Dominancein a Single-GateABCA BCAsa1Bsa1Csa1Asa0Bsa0Csa00 000 101 001 1111111000A sa0 B sa0 C sa0 C sa1 -A sa1C sa1 -B sa1*Fault equivalence:*Fault dominance:*A-sa0,B-sa0,and C-sa1 need notto be considered.Chap1.Fundamentals.81Fault CollapsingFor each n-input gate,we only need to consider n+1 faultsChap1.Fundamentals.82Prime Faulta is a prime fault if every fault that is dominated by a is also equivalent to a Representative Set of Prime Fault(RSPF)A set that consists of exactly one prime fault from each equivalence class of prime faultsTrue minimal RSPF is difficult to findChap1.Fundamentals.83Why Fault Collapsing?#oftotal faults#ofequivalent faults#ofprime faults160%40%*Memory&CPU-Time saving=To ease the burden for test generation and fault simulation in testingChap1.Fundamentals.84Fault Collapsing fora Combinatio
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