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Click to edit Master title,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,1: Circuits & Layout,*,CMOS VLSI Design,4th Ed.,Lecture 1: Circuits & Layout,1,1: Circuits & Layout,Outline,A Brief History,CMOS Gate Design,Pass Transistors,CMOS Latches & Flip-Flops,Standard Cell Layouts,Stick Diagrams,2,1: Circuits & Layout,A Brief History,1958: First integrated circuit,Flip-flop using two transistors,Built by Jack,Kilby,at Texas Instruments,2010,Intel Core i7,m,processor,2.3 billion transistors,64,Gb,Flash memory, 16 billion transistors,Courtesy Texas Instruments,Trinh09, 2009 IEEE.,3,1: Circuits & Layout,Growth Rate,53% compound annual growth rate over 50 years,No other technology has grown so fast so long,Driven by miniaturization of transistors,Smaller is cheaper, faster, lower in power!,Revolutionary effects on society,Moore65,Electronics Magazine,4,1: Circuits & Layout,Annual Sales,10,19,transistors manufactured in 2008,1 billion for every human on the planet,5,1: Circuits & Layout,Invention of the Transistor,Vacuum tubes ruled in first half of 20,th,century Large, expensive, power-hungry, unreliable,1947: first point contact transistor,John,Bardeen,and Walter,Brattain,at Bell Labs,See,Crystal Fire,by Riordan,Hoddeson,AT&T Archives. Reprinted with permission.,6,1: Circuits & Layout,Transistor Types,Bipolar transistors,npn or,pnp,silicon structure,Small current into very thin base layer controls large currents between emitter and collector,Base currents limit integration density,Metal Oxide Semiconductor Field Effect Transistors,nMOS and pMOS MOSFETS,Voltage applied to insulated gate controls current between source and drain,Low power allows very high integration,7,1: Circuits & Layout,1970s processes usually had only nMOS transistors,Inexpensive, but consume power while idle,1980s-present: CMOS processes for low idle power,MOS Integrated Circuits,Intel 1101 256-bit SRAM,Intel 4004 4-bit,m,Proc,Vadasz69, 1969 IEEE.,Intel Museum.,Reprinted with permission.,8,1: Circuits & Layout,Moores Law: Then,1965: Gordon Moore plotted transistor on each chip,Fit straight line on,semilog,scale,Transistor counts have doubled every 26 months,Integration Levels,SSI,: 10 gates,MSI,: 1000 gates,LSI,: 10,000 gates,VLSI,: 10k gates,Moore65,Electronics Magazine,9,1: Circuits & Layout,And Now,10,1: Circuits & Layout,Feature Size,Minimum feature size shrinking 30% every 2-3 years,11,1: Circuits & Layout,Corollaries,Many other factors grow exponentially,Ex: clock frequency, processor performance,12,1: Circuits & Layout,CMOS Gate Design,Activity:,Sketch a 4-input CMOS NOR gate,13,1: Circuits & Layout,Complementary CMOS,Complementary CMOS logic gates,nMOS,pull-down network,pMOS,pull-up network,a.k.a. static CMOS,Pull-up OFF,Pull-up ON,Pull-down OFF,Z (float),1,Pull-down ON,0,X (crowbar),14,1: Circuits & Layout,Series and Parallel,nMOS: 1 = ON,pMOS: 0 = ON,Series,: both must be ON,Parallel,: either can be ON,15,1: Circuits & Layout,Conduction Complement,Complementary CMOS gates always produce 0 or 1,Ex: NAND gate,Series nMOS: Y=0 when both inputs are 1,Thus Y=1 when either input is 0,Requires parallel pMOS,Rule of,Conduction Complements,Pull-up network is complement of pull-down,Parallel - series, series - parallel,16,1: Circuits & Layout,Compound Gates,Compound gates,can do any inverting function,Ex:,17,1: Circuits & Layout,Example: O3AI,18,1: Circuits & Layout,Signal Strength,Strength,of signal,How close it approximates ideal voltage source,V,DD,and GND rails are strongest 1 and 0,nMOS pass strong 0,But degraded or weak 1,pMOS pass strong 1,But degraded or weak 0,Thus nMOS are best for pull-down network,19,1: Circuits & Layout,Pass Transistors,Transistors can be used as switches,20,1: Circuits & Layout,Transmission Gates,Pass transistors produce degraded outputs,Transmission gates,pass both 0 and 1 well,21,1: Circuits & Layout,Tristates,Tristate buffer,produces Z when not enabled,EN,A,Y,0,0,Z,0,1,Z,1,0,0,1,1,1,22,1: Circuits & Layout,Nonrestoring Tristate,Transmission gate acts as tristate buffer,Only two transistors,But,nonrestoring,Noise on A is passed on to Y,23,1: Circuits & Layout,Tristate Inverter,Tristate inverter produces restored output,Violates conduction complement rule,Because we want a Z output,24,1: Circuits & Layout,Multiplexers,2:1 multiplexer chooses between two inputs,S,D1,D0,Y,0,X,0,0,0,X,1,1,1,0,X,0,1,1,X,1,25,1: Circuits & Layout,Gate-Level Mux Design,How many transistors are needed?,20,26,1: Circuits & Layout,Transmission Gate Mux,Nonrestoring mux uses two transmission gates,Only 4 transistors,27,1: Circuits & Layout,Inverting Mux,Inverting multiplexer,Use compound AOI22,Or pair of tristate inverters,Essentially the same thing,Noninverting multiplexer adds an inverter,28,1: Circuits & Layout,4:1 Multiplexer,4:1 mux chooses one of 4 inputs using two selects,Two levels of 2:1,muxes,Or four tristates,29,1: Circuits & Layout,D Latch,When CLK = 1, latch is,transparent,D flows through to Q like a buffer,When CLK = 0, the latch is,opaque,Q holds its old value independent of D,a.k.a.,transparent latch,or,level-sensitive latch,30,1: Circuits & Layout,D Latch Design,Multiplexer chooses D or old Q,31,1: Circuits & Layout,D Latch Operation,32,1: Circuits & Layout,D Flip-flop,When CLK rises, D is copied to Q,At all other times, Q holds its value,a.k.a.,positive edge-triggered flip-flop,master-slave flip-flop,33,1: Circuits & Layout,D Flip-flop Design,Built from master and slave D latches,34,1: Circuits & Layout,D Flip-flop Operation,35,1: Circuits & Layout,Race Condition,Back-to-back flops can malfunction from clock skew,Second flip-flop fires late,Sees first flip-flop change and captures its result,Called,hold-time failure,or,race condition,36,1: Circuits & Layout,Nonoverlapping Clocks,Nonoverlapping clocks can prevent races,As long as nonoverlap exceeds clock skew,We will use them in this class for safe design,Industry manages skew more carefully instead,37,1: Circuits & Layout,Gate Layout,Layout can be very time consuming,Design gates to fit together nicely,Build a library of standard cells,Standard cell design methodology,V,DD,and GND should abut (standard height),Adjacent gates should satisfy design rules,nMOS at bottom and pMOS at top,All gates include well and substrate contacts,38,1: Circuits & Layout,Example: Inverter,39,1: Circuits & Layout,Example: NAND3,Horizontal N-diffusion and p-diffusion strips,Vertical polysilicon gates,Metal1 V,DD,rail at top,Metal1 GND rail at bottom,32,l,by 40,l,40,1: Circuits & Layout,Stick Diagrams,Stick diagrams,help plan layout quickly,Need not be to scale,Draw with color pencils or dry-erase markers,41,1: Circuits & Layout,Wiring Tracks,A,wiring track,is the space required for a wire,4,l,width, 4,l,spacing from neighbor = 8,l,pitch,Transistors also consume one wiring track,42,1: Circuits & Layout,Well spacing,Wells must surround transistors by 6,l,Implies 12,l,between opposite transistor flavors,Leaves room for one wire track,43,1: Circuits & Layout,Area Estimation,Estimate area by counting wiring tracks,Multiply by 8 to express in,l,44,1: Circuits & Layout,Example: O3AI,Sketch a stick diagram for O3AI and estimate area,45,1: Circuits & Layout,
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