电子时钟的深入设计方案

电子时钟设计电子时钟设计设计要求n设计一个电子时钟。n要求可以显示时、分、秒。n用户可以设置时间。系统组成 系统可以分为以下模块：n1.10进制可预置计数器模块n2.6进制可预置计数器模块n3.24进制可预置计数器模块n4.LED译码模块系统组成方框图 置数按键控制按键基准时钟计数器动态显示译码显示1.10进制可预置计数器模块n时钟由时、分、秒组成，分、秒都为60进制。n由于需要使用LED显示时间，所以采用的计数器应该是10进制的，从而方便译码模块的通用。n而60进制计数器可以由10进制计数器和6进制计数器组成。2.6进制可预置计数器模块n要组成一个可预置的60进制计数器，还需要一个6进制的计数器，n使用10进制的进位作为6进制的计数器的时钟信号可以组成一个60进制的计数器。24进制可预置计数器模块n时钟的小时是24进制的，所以必须设计一个24进制的可预置计数器。n显然，24进制计数器不可以使用6进制计数器和4进制计数器组成，n因为这样做的24进制计数器将给译码带来麻烦。4.译码显示模块n一共有6个LED需要显示，所以需要6个译码模块。电子时钟设计与仿真 10进制计数器VHDL程序n-文件名：counter10.vhd。n-功能：10进制计数器，有进位Cn-最后修改日期：2004.3.20nlibrary IEEE;nuse IEEE.STD_LOGIC_1164.ALL;nuse IEEE.STD_LOGIC_ARITH.ALL;nuse IEEE.STD_LOGIC_UNSIGNED.ALL;nentity counter10 isn Port(clk:in std_logic;n reset:in std_logic;n din:in std_logic_vector(3 downto 0);n dout:out std_logic_vector(3 downto 0);n c:out std_logic);nend counter10;narchitecture Behavioral of counter10 isn signal count:std_logic_vector(3 downto 0);nbeginn dout=count;nprocess(clk,reset,din)nbeginn if reset=0then count=din;c=0;n elsif rising_edge(clk)thenn if count=1001 then count=0000;c=1;n else count=count+1;c=0;n end if;n end if;n end process;nend Behavioral;10进制计数器仿真6进制计数器VHDL程序 n-文件名：counter6.vhd。n-功能：6进制计数器，有进位Cn-最后修改日期：2004.3.20nlibrary IEEE;nuse IEEE.STD_LOGIC_1164.ALL;nuse IEEE.STD_LOGIC_ARITH.ALL;nuse IEEE.STD_LOGIC_UNSIGNED.ALL;nentity counter6 isn Port(clk:in std_logic;n reset:in std_logic;n din:in std_logic_vector(2 downto 0);n dout:out std_logic_vector(2 downto 0);n c:out std_logic);nend counter6;narchitecture Behavioral of counter6 isnsignal count:std_logic_vector(2 downto 0);nbeginn nprocess(clk,reset,din)nbeginn if reset=0 then count=din;c=0;n elsif rising_edge(clk)thenn if count=101 then count=000;c=1;n else count=count+1;c=0;n end if;n end if;nend process;ndout=count;nend Behavioral;6进制计数器仿真 24进制计数器VHDL程序n-文件名：counter24.vhd。n-功能：24进制计数器。n-最后修改日期：2004.3.20nlibrary IEEE;nuse IEEE.STD_LOGIC_1164.ALL;nuse IEEE.STD_LOGIC_ARITH.ALL;nuse IEEE.STD_LOGIC_UNSIGNED.ALL;nentity counter24 isn Port(clk:in std_logic;n reset:in std_logic;n din:in std_logic_vector(5 downto 0);n dout:out std_logic_vector(5 downto 0);nend counter24;narchitecture Behavioral of counter24 isnsignal count:std_logic_vector(5 downto 0);nbeginnprocess(clk,reset,din)nbeginn if reset=0 then count=din;n elsif rising_edge(clk)then n if count(3 downto 0)=1001 then count(3 downto 0)=0000;ncount(5 downto 4)=count(5 downto 4)+1;n else count(3 downto 0)=count(3 downto 0)+1;n end if;n if count=100011 then count=000000;n end if;n end if;nend process;ndout dout dout dout dout dout dout dout dout dout dout dout=1111111;nend case;nend process;nend Behavioral;顶层设计VHDL程序n-文件名：clock.vhd。n-功能：时钟的顶层设计。n-最后修改日期：2004.3.20nlibrary IEEE;nuse IEEE.STD_LOGIC_1164.ALL;nuse IEEE.STD_LOGIC_ARITH.ALL;nuse IEEE.STD_LOGIC_UNSIGNED.ALL;nentity clock isn Port(clk:in std_logic;-1Hzn reset:in std_logic;-复位信号n dins:in std_logic_vector(6 downto 0);-秒钟预置n dinm:in std_logic_vector(6 downto 0);-分钟预置n dinh:in std_logic_vector(5 downto 0);-时钟预置n secondl:out std_logic_vector(6 downto 0);-秒钟低位输出n secondh:out std_logic_vector(6 downto 0);-秒钟高位输出n minutel:out std_logic_vector(6 downto 0);-分钟低位输出n minuteh:out std_logic_vector(6 downto 0);-分钟高位输出nn hourl:out std_logic_vector(6 downto 0);-小时低位输出n hourh:out std_logic_vector(6 downto 0);-小时高位输出nend clock;narchitecture Behavioral of clock isncomponent counter10 isnPort(clk:in std_logic;n reset:in std_logic;n din:in std_logic_vector(3 downto 0);n dout:out std_logic_vector(3 downto 0);n c:out std_logic);nend component;ncomponent counter6 isnPort(clk:in std_logic;n reset:in std_logic;n din:in std_logic_vector(2 downto 0);n dout:out std_logic_vector(2 downto 0);n c:out std_logic);nend component;ncomponent counter24 isn Port(clk:in std_logic;n reset:in std_logic;n din:in std_logic_vector(5 downto 0);n dout:out std_logic_vector(5 downto 0);nend component;nncomponent decoder isnPort(din:in std_logic_vector(3 downto 0);n dout:out std_logic_vector(6 downto 0);nend component;nsignal c1,c2,c3,c4:std_logic;nsignal doutsl,doutml:std_logic_vector(3 downto 0);nsignal doutsh,doutmh:std_logic_vector(2 downto 0);nsignal douth:std_logic_vector(5 downto 0);nsignal rdoutsh,rdoutmh:std_logic_vector(3 downto 0);nsignal rdouth:std_logic_vector(7 downto 0);nbeginnrdoutsh=0&doutsh;-将秒钟高位数据变为4位，再进行译码nrdoutmh=0&doutmh;-将分钟高位数据变为4位，再进行译码nrdouth clk,reset=reset,n din=dins(3 downto 0),dout=doutsl,c=c1);n u2:counter6 port map(clk=c1,reset=reset,n din=dins(6 downto 4),dout=doutsh,c=c2);n u3:counter10 port map(clk=c2,reset=reset,din=dinm(3 downto 0),ndout=doutml,c=c3);n u4:counter6 port map(clk=c3,reset=reset,n din=dinm(6 downto 4),dout=doutmh,c=c4);nnu5:counter24 port map(clk=c4,reset=reset,n din=dinh,dout=douth);nu6:decoder port map(din=doutsl,dout=secondl);-秒的低位nu7:decoder port map(din=rdoutsh,dout=secondh);-秒的高位nu8:decoder port map(din=doutml,dout=minutel);-分的低位nu9:decoder port map(din=rdoutmh,dout=minuteh);-分的高位nu10:decoder port map(din=rdouth(3 downto 0),dout=hourh);-时的低位nu11:decoder port map(din=rdouth(7 downto 4),dout=hourl);-时的高位nend Behavioral;顶层设计仿真