数字钟电路原理图程序

数字钟电路原理图程序清单*顶层程序描述*程序：TIMER_SET.VHDlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity timer_set is port(cp:in std_logic; -CLOCK segout:out std_logic_vector(7 downto 0); -SEG7 DISPLAY O/P selout:out std_logic_vector(5 downto 0); -SELECT SEG7 O/P numout:out std_logic_vector(3 downto 0); -NUMBER DISPLAY SIGNAL key:in std_logic_vector(2downto0); -TIMER&ADJUST&CLRend timer_set;architecture behavioral of timer_set is component counter60 port(cp :in std_logic; bin :out std_logic_vector(5 downto 0); s :in std_logic; clr :in std_logic; ec :in std_logic; cy60:out std_logic); end component; component counter24 port(cp :in std_logic; bin :out std_logic_vector(5 downto 0); s :in std_logic; clr :in std_logic; ec :in std_logic; cy24:out std_logic); end component; component free_counter port(cp :in std_logic; dbs :in std_logic_vector(5 downto 0); dbm :in std_logic_vector(5 downto 0); dbh :in std_logic_vector(5 downto 0); state :in std_logic_vector(1 downto 0); sec :out std_logic; sample :out std_logic; glitter:out std_logic; bin :out std_logic_vector(5 downto 0); enb :out std_logic_vector(2 downto 0); sel :out std_logic_vector(5 downto 0); match :out std_logic; s :out std_logic_vector(2 downto 0); end component; component binary_bcd port(bin:in std_logic_vector(5 downto 0); bcd:out std_logic_vector(7 downto 0); end component; component seven_segment port(num:in std_logic_vector(3 downto 0); seg:out std_logic_vector(6 downto 0); end component; component debounce port(cp :in std_logic; sample :in std_logic; key :in std_logic_vector(2 downto 0); dly_out:out std_logic); end component; component differential port(cp :in std_logic; dly_out :in std_logic; diff:out std_logic); end component; component timerset port(cp :in std_logic; diff :in std_logic; key :in std_logic_vector(2 downto 0); state:out std_logic_vector(1 downto 0); end component; signal bin:std_logic_vector(5 downto 0); -BINARYO/P signal dbs:std_logic_vector(5 downto 0); -BINARY SEC O/P signal dbm:std_logic_vector(5 downto 0); -BINARY MIN O/P signal dbh:std_logic_vector(5 downto 0); -BINARY HR O/P signal enb:std_logic_vector(2 downto 0); -ENABLE HR&MIN&SEC O/P signal sec:std_logic; -1HZ脉冲波形 signal bcd:std_logic_vector(7 downto 0); signal clr:std_logic; -清楚信号 signal cys,cym,cyh:std_logic; -小时、小时、HR进位信号 signal s:std_logic_vector(2 downto 0); -选择SEGMENT7 signal num:std_logic_vector(3 downto 0); -NUMBER DISPLAY SIGNAL signal seg:std_logic_vector(6 downto 0); -SEG7 DISPLAY SIGNAL signal sel:std_logic_vector(5 downto 0); -SELECT SEG7 SIGNAL signalsample,dly_out,diff:std_logic; -BINARY signalstate:std_logic_vector(1downto0); -TIMER设定状态 -11计时 -10调秒 -01调分 -00调时 signal match:std_logic; signal glitter:std_logic; -闪烁beginconnection:block signal adj,ecs,ecm,ech,sc:std_logic;begin u1:counter60 port map(cp,dbs,enb(0),clr,ecs,cys); u2:counter60 port map(cp,dbm,enb(1),clr,ecm,cym); u3:counter24 port map(cp,dbh,enb(2),clr,ech,cyh); u4:free_counter port map(cp,dbs,dbm,dbh,state,sec,sample,glitter,bin,enb,sel,match,s); u5:binary_bcd port map(bin,bcd); u6:seven_segment port map(num,seg); u7:debounce port map(cp,sample,key,dly_out); u8:differential port map(cp,dly_out,diff); u9:timerset port map(cp,diff,key,state); clr= not key(0); -复位计时 sc=state(1)andstate(0); -计时状态 adj=secand(notsc)andkey(1); -adjust ecs=(sec and sc)or(adj and state(1)and not state(0); -计秒 ecm=(cys and sc)or(adj and not state(1)and state(0); -计分 ech=(cym and sc)or(adj and not state(1)and not state(0); -计时 selout= sel; gen:for i in 0 to 6 generate segout(i)=seg(i)and(sc or(glitter or not match); end generate; segout(7)=0; numout= num;end block connection;select_bcd:blockbegin num= bcd(3 downto 0)when (s=0 or s=2 or s= 4)else bcd(7 downto 0);end block select_bcd;end behavioral;*子模块描述*COUNTER24.VHD - 24进制计数器模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity counter24 is port(cp:in std_logic; -时钟脉冲 bin:out std_logic_vector(5 downto 0); -二进制 s:in std_logic; -输出激活信号 clr:in std_logic; -清除信号 ec:in std_logic; -使能计数信号 cy24:out std_logic); -计数24进位信号end counter24;architecture behavioral of counter24 is signal q:std_logic_vector(4 downto 0); signal rst,dly:std_logic;begin -计数24 process(cp,rst) begin if rst=1then q=00000; -复位计数器 elsif cpevent and cp=1 then dly=q(4); if ec=1then q=q+1; -计数值加1 end if; end if; end process; cy24=not q(4) and dly; -进位信号微分 rst=1when q=24 or clr=1else0; -复位信号设定 bin =(0&q)when s=1else000000; -计数输出end behavioral;COUNTER60.VHD -60进制计数器模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity counter60 is port(cp:in std_logic; -时钟脉冲 bin:out std_logic_vector(5 downto 0); -二进制 s:in std_logic; -输出激活信号 clr:in std_logic; -清除信号 ec:in std_logic; -使能计数信号 cy60:out std_logic); -计数60进位信号 end counter60;architecture behavioral of counter60 is signal q:std_logic_vector(5 downto 0); signal rst,dly:std_logic;begin -计数60 process(cp,rst) begin if rst=1then q=000000; -复位计数器 elsif cpevent and cp=1then dly=q(5); if ec=1then q=q+1; -计数值加1 end if; end if; end process; cy60=not q(5) and dly; -进位信号微分 rst=1when q=60 or clr=1 else -复位信号设定 0; bin=q when s=1 else -计数输出 000000;end behavioral;FREE_COUNTER.VHD -自由计数器&产生扫描信号library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity free_counter is port(cp:in std_logic; dbs:in std_logic_vector(5 downto 0); dbm:in std_logic_vector(5 downto 0); dbh:in std_logic_vector(5 downto 0); state:in std_logic_vector(1 downto 0); sec:out std_logic; sample:out std_logic; glitter:out std_logic; bin:out std_logic_vector(5 downto 0); enb:out std_logic_vector(2 downto 0); sel:out std_logic_vector(5 downto 0); match:out std_logic; s:out std_logic_vector(2 downto 0);end free_counter;architecture behavioral of free_counter is signal q:std_logic_vector(24 downto 0); signal dly,sdly:std_logic; signal ss:std_logic_vector(2 downto 0); signal en:std_logic_vector(2 downto 0);begin -计数器计数 process(cp) begin if cpevent and cp=1then dly=q(21); sdly=q(14); q=q+1; -计数 end if; end process; glitter=q(21); sec=q(21)and not dly; -微分产生1HZ ss=q(15 downto 13); -about250HZ sample=q(14)and not sdly; -取样信号 -扫描信号 sel=111110when ss=0 else 111101when ss=1 else 111001when ss=2 else 110111when ss=3 else 101111when ss=4 else 011111when ss=5 else 111111; en=001when(ss=0 or ss=1)else 010when(ss=2 or ss=3)else 100when(ss=4 or ss=5)else 000; bin=dbs when en=001else -选择秒、分、时 dbm when en=010else dbh when en=100else 000000; match=1when(ss=0 or ss=1)and state=10)else 1when(ss=2 or ss=3) and state=01)else 1when(ss=4 or ss=5)and state=00)else 0; s=ss; enb=en;end behavioral;BINARY_BCD.VHD -二进制与BCD码转换模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity binary_bcd is port(bin:in std_logic_vector(5 downto 0); bcd:out std_logic_vector(7 downto 0););end binary_bcd;architecture behavioral of binary_bcd isbegin -二进制与BCD码的转换 bcdSegment7Codebegin seg=0111111when num=0 else 0000110when num=1 else 1011011when num=2 else 1001111when num=3 else 1100110when num=4 else 1101101when num=5 else 1111101when num=6 else 0000111when num=7 else 1111111when num=8 else 1101111when num=9 else 1110111when num=10 else 1111100when num=11 else 0111001when num=12 else 1011110when num=13 else 1111001when num=14 else 1110001when num=15 else 0000000;end behavioral;DEBOUNCE.VHD -消除弹跳电路模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity debounce is port(cp:in std_logic; sample:in std_logic; key:in std_logic_vector(2 downto 0); dly_out:out std_logic);end debounce;architecture behavioral of debounce is signal d0,d1,s,r,dly,ndly:std_logic;begin process(cp) begin if cpevent and cp=1then if sample=1then d1=d0;d0=key(2); -二级延迟 s=d0 and d1; r=not d0 and not d1; end if; end if; end process; dly=r nor ndly; -RS触发器ndly=s nor dly; dly_out=dly; -RS触发器输出end behavioral;DIFFERENTIAL.VHD -BCD码选择器模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity differential is port(cp:in std_logic; dly_out:in std_logic; diff:out std_logic); -SEG7 DISPLAY O/Pend differential;architecture behavioral of differential is signal d1,d0:std_logic;begin process(cp) begin if cpevent and cp=1then d1=d0;d0=dly_out; -二级延迟 end if; end process; diff=d0 and not d1; -微分end behavioral;TIMERSET.VHD -预置数模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity timerset is -SEC&Min&Hr Adjustment? port(cp:in std_logic; diff:in std_logic; key:in std_logic_vector(2 downto 0); state:out std_logic_vector(1 downto 0);end timerset;architecture behavioral of timerset is signal q:std_logic_vector(2 downto 0); signal set,ec:std_logic;begin process(cp) begin if set=1then q=011; elsif cpevent and cp=1 then if ec=1then q=q-1; end if; end if; end process; set=1when q=7 else 0; ec=diff and key(2); -TIMER KEY 微分 state=q(1 downto 0); -Record Timer Stateend behavioral;v