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Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,精品文档,*,*,Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,精品文档,Field Effect Transistors(FETs),In a field effect transistor,current flow through a semiconductor channel is controlled by the application of an electric field(voltage)perpendicular to the direction of current flow.,We consider the MOSFET(MOST)-the metal oxide semiconductor(field effect)transistor.,Field Effect Transistors(FETs,Field Effect Transistors(FETs),In a depletion mode MOSFET a channel is built in so that conduction occurs with no control voltage applied.,We consider an n-channel enhancement mode device which has no built-in conduction channel.,Field Effect Transistors(FETs,N-channel enhancement mode MOSFET(schematic),Oxide(SiO,2,),n,+,n,+,p-type silicon,Gate(G),Drain(D),Source(S),N-channel enhancement mode MOS,Symbol for N-channel enhancement mode MOSFET,Note connection to substrate shown,Symbol for N-channel enhanceme,Symbol for N-channel enhancement mode MOSFET,Note connection to substrate shown,G,S,D,Symbol for N-channel enhanceme,N-channel enhancement mode MOSFET:outline of operation,VGS=0,little or no current can flow S D,back to back p-n junctions.,As a positive VGS is applied,holes in the p-region are repelled.,As VGS increases further,electrons are attracted from the substrate towards the positive gate.,An inversion layer of mobile electrons forms near the silicon surface.,N-channel enhancement mode MOS,N-channel enhancement mode MOSFET with inversion layer,Source(S),Oxide(SiO,2,),n,+,n,+,p-type silicon,Gate(G),Drain(D),Inversion layer(conduction channel),N-channel enhancement mode MOS,N-channel enhancement mode MOSFET:outline of operation,This inversion layer is effectively n-type.,Electrons can carry current in an continuous n-type path(or channel)from source to drain.,The conduction channel forms when VGS attains a threshold voltage,VT,N-channel enhancement mode MOS,N-channel enhancement mode MOSFET,The value of VT is determined by the device process and the level of the p-type(substrate)doping.,Note that an n-channel device is formed with a p-type substrate.,N-channel enhancement mode MOS,N-channel enhancement mode MOSFET,As VGS increases further,more electrons are drawn into the inversion layer and the channel resistance decreases(The device operates as a voltage controlled resistor).,However,N-channel enhancement mode MOS,N-channel enhancement mode MOSFET,The voltage between gate and channel varies from VGS at the source end to VGS-VDS at the drain end.,Thus as the voltage at the drain end,VDS,is increased the effective gate-channel voltage(vertical field)is decreased.,N-channel enhancement mode MOS,N-channel enhancement mode MOSFET,This causes the carrier density at the drain end of the inversion layer to decrease.,The current levels off or saturates.,The FET is then said to have entered its saturation region(This expression had a different meaning in our discussion of BJTs).,N-channel enhancement mode MOS,N-channel enhancement mode MOSFET,The boundary where saturation starts occurs at(VGS VDS)=VT.,i.e.VDS=(VGS VT),Ideally we would want a further increase in VDS to have no effect on the drain current ID,N-channel enhancement mode MOS,N-channel enhancement mode MOSFET,In practice as VDS is increased further ID also increases.,This is due to a reduction in the effective channel length with VDS.,We note,for design purposes,that the gate current(IG)is effectively zero.(We have an insulating oxide region),N-channel enhancement mode MOS,N-channel Depletion mode MOSFET,In a depletion mode MOST a channel is built into the device.,Conduction occurs at VDS=0.,(The threshold voltage VT is negative),N-channel Depletion mode MOSFE,Symbol for N-channel depletion mode MOSFET,Connection to substrate shown.,The solid line indicates that a physical channel exists at VGS=0.,Symbol for N-channel depletion,P-channel devices,These are widely used,particularly in Complementary MOS(C-MOS)circuits.,Electron mobility is larger than hole mobility so n-channel devices are faster,i.e.they have a higher frequency response.,P-channel devicesThese are wid,Plots and Equations,Enhancement mode,VT 2 V,V,DS,=V,GS,-V,T,Plots and Equations,Enhanceme,FET Plots and equations,The FET is a voltage controlled device.,The control parameter is VGS compare with IB in the BJT.,FET Plots and equationsThe FET,Loose equivalences,FET,Drain,Source,Gate,BJT,Collector,Emitter,Base,Loose equivalencesFETBJT,Plots and Equations,V,DS,=V,GS,-V,T,Saturation region,Plots and EquationsVDS=VGS-,Plots and Equations,V,DS,=V,GS,-V,T,Triode region,Plots and EquationsVDS=VGS-,Transfer Characteristic,Gives the relationship between ID and VGS in the saturation(constant current)regime.,e.g.for an enhancement mode device,V,T,V,GS,I,D,Transfer CharacteristicGives t,Transfer Characteristic,This I-V curve in the sat
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