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Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,*,2009 Altera Corporation,Altera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation,2009 Altera Corporation,*,Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,*,2009 Altera Corporation,Altera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation,2009 Altera Corporation,Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,Quartus,II Software Design Series:Timing Analysis,-,Timing analysis basics,2,Objectives,Display a complete understanding of timing analysis,3,How does timing verification work?,Every device path in design must be analyzed with respect to timing specifications/requirements,Catch timing-related errors faster and easier than gate-level simulation&board testing,Designer must enter timing requirements&exceptions,Used to guide fitter during placement&routing,Used to compare against actual results,IN,CLK,OUT,D,Q,CLR,PRE,D,Q,CLR,PRE,combinational delays,CLR,4,Timing Analysis Basics,Launch vs.latch edges,Setup&hold times,Data&clock arrival time,Data required time,Setup&hold slack analysis,I/O analysis,Recovery&removal,Timing models,5,Path&Analysis Types,Three types of Paths:,Clock Paths,Data Path,Asynchronous Paths*,Clock Paths,Async Path,Data Path,Async Path,D,Q,CLR,PRE,D,Q,CLR,PRE,Two types of Analysis:,Synchronous clock&data paths,Asynchronous*clock&async paths,*,Asynchronous refers to signals feeding the asynchronous control ports of the registers,6,Launch&Latch Edges,CLK,Launch Edge,Latch Edge,Data Valid,DATA,Launch Edge:the edge which“launches”the data from source register,Latch Edge:the edge which“latches”the data at destination register(with respect to the launch edge,selected by timing analyzer;typically 1 cycle),7,Setup&Hold,Setup:The minimum time data signal must be stable,BEFORE clock edge,Hold:The minimum time data signal must be stable,AFTER clock edge,D,Q,CLR,PRE,CLK,T,h,Valid,DATA,T,su,CLK,DATA,Together,the setup time and hold time form a Data Required Window,the time around a clock edge in which data must be stable.,8,Data Arrival Time,Data Arrival Time=launch edge+T,clk1,+T,co,+T,data,CLK,REG1.CLK,T,clk1,Data Valid,REG2.D,T,data,Launch,Edge,Data Valid,REG1.Q,T,co,The time for data to arrive at destination registers D input,REG1,PRE,D Q,CLR,REG2,PRE,D Q,CLR,Comb.,Logic,T,clk1,T,CO,T,data,9,Clock Arrival Time,Clock Arrival Time=latch edge+T,clk2,CLK,REG2.CLK,T,clk2,Latch,Edge,The time for clock to arrive at destination registers clock input,REG1,PRE,D Q,CLR,REG2,PRE,D Q,CLR,Comb.,Logic,T,clk2,10,Data Required Time-Setup,Data Required Time=Clock Arrival Time,-,T,su,-Setup Uncertainty,CLK,REG2.CLK,T,clk2,Latch,Edge,The minimum time required for the data to get latched into the destination register,T,su,Data Valid,REG2.D,Data must be valid here,REG1,PRE,D Q,CLR,REG2,PRE,D Q,CLR,Comb.,Logic,T,clk2,T,su,11,Data Required Time-Hold,Data Required Time=Clock Arrival Time+T,h,+Hold Uncertainty,CLK,REG2.CLK,T,clk2,Latch,Edge,The minimum time required for the data to get latched into the destination register,T,h,Data must,remain valid,to here,Data Valid,REG2.D,REG1,PRE,D Q,CLR,REG2,PRE,D Q,CLR,Comb.,Logic,T,clk2,T,h,12,T,clk2,Setup Slack,REG2.CLK,The margin by which the setup timing requirement is met.It ensures launched data arrives in time to meet the latching requirement.,T,su,CLK,REG1.CLK,T,clk1,Data Valid,REG2.D,T,data,Data Valid,REG1.Q,T,co,Setup,Slack,Launch,Edge,Latch,Edge,REG1,PRE,D Q,CLR,REG2,PRE,D Q,CLR,Comb.,Logic,T,clk1,T,CO,T,data,T,clk2,T,su,13,Setup Slack(contd),Positive slack,Timing requirement met,Negative slack,Timing requirement not met,Setup Slack=Data Required Time,Data Arrival Time,14,Hold Slack,REG2.CLK,T,clk2,The margin by which the hold timing requirement is met.It ensures latch data is not corrupted by data from another launch edge.,T,h,CLK,REG1.CLK,T,clk1,Data Valid,REG2.D,T,data,Data Valid,REG1.Q,T,co,Hold,Slack,Latch,Edge,Next Launch,Edge,REG1,PRE,D Q,CLR,REG2,PRE,D Q,CLR,Comb.,Logic,T,clk1,T,CO,T,data,T,clk2,T,h,15,Hold Slack(contd),Positive slack,Timing requirement met,Negative slack,Timing requirement not met,Hold Slack=Data Arrival Time,Data Required Time,16,FPGA/CPLD or ASSP,ASSP or FPGA/CPLD,I/O Analysis,Analyzing I/O performance in a synchronous design uses the same slack equations,Must include external device&PCB timing parameters,reg1,PRE,D Q,CLR,reg2,PRE,D Q,CLR,C,L,*,T,data,T,clk1,T,clk2,T,CO,T,su,/T,h,OSC,Data Arrival Path,Data Arrival Path,Data Required Path,*,Represents delay due to capacitive loading,17,Recovery&Removal,Recovery:The minimum time an asynchronous signal must,be stable BEFORE clock edge,Remova
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