BIOS POST CODE简介

单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,Confidential Document,46,BIOS POST CODE簡介,Edit By Gemi 2005.12,1,目錄,BIOS的定義,BIOS的作用,BIOS的三大品牌簡介,BIOS POST的簡易流程,BIOS POST CODE的定義,AWARD POST CODE,AMI POST CODE,BIOS 的定義,BIOS,是,Basic Input/Output System,的縮寫,中文就是基本輸出入系統,BIOS,本身就是一套獨立且完整的控管程式,可說是用來控制硬體動作的韌體程式,也就是硬體與作業系統間的媒介軟體。,BIOS的存儲介質我們稱之為ROM，ROM又可以分為如下几類：,PROM（Programmable ROM）可編程存儲器，出厰時每個字節數據都是FF，可以用燒錄器將數據寫入，但只能寫入一次。,Mask ROM出厰時就已經有特定的程序/數據，內容無法自行修改或燒錄。,EPROM（Erasable PROM）PROM的改良，可使用紫外線照射使所有字節恢复成FF。用戶可以重新燒錄新的程序或數據。,Flash ROM 快速只讀存儲器，是當今最常用的內存種類。其特點如下：,1. 先前寫入的數據無法被擦除或破坏，即時關掉電源之后內容仍舊存在，這一定是ROM的特性。,2. 不過在特殊工具程序的配合下以及相關硬件的設置在某種特定的電壓下，內部存儲的程序代碼或數據可以被擦除，并且可以重新修改寫入新版本的程序或數據。,3.讀取的最小單位是一個Byte，但擦除或寫入的單位是以一個Block，Block的大小從4K，8K到16K不等。,BIOS 的主要作用,BIOS的主要功能如下：,POST開机自我檢測,系統硬体置,系統組態分析,載入操作系統,POST,是,Power On Self Test,縮寫主要任務是用來測試安裝於主機板上的各種硬體,如偵測到有硬體錯誤,即會依主機板廠商設計發出警示聲,或是產生,Post Error Code,輸出至位址,Port 80H。,重新配置各個硬體的設定值,包括中斷位址表,系統資源等。,開機後重新進行整體系統的組態分析,也就是自動偵測系統中所安裝硬體與配置是否正確。,執行完前前三項工作之後,會進入磁碟機中搜尋作業系統開機磁區,將開機所需開機程序載入主記憶體,以執行進一步系統開機程序。,BIOS的三大品牌簡介,Award BIOS,為桌上型電腦,(,特別是主機板市場,),佔有率第一名,其特色為低價,低授權金且功能齊全而廣受喜愛。,(AMI,American Megatrends Inc.),美商安邁公司於,1985,年,由,S.Shankar,與一些滿懷理想的工程師所創立,.,主要業務為,BIOS,研發,USB,硬體週邊韌體, RAID,控制卡韌體等相關技術支援與服務,.,其,BIOS,業務至今提供,55%,的,OEM,廠商使用,.,主要客戶,Dell,HP,NECGetaway,等大廠桌上型及筆記型電腦領域,.,(Phoenix Technology 鳳凰科技)現今依舊是筆記型電腦用BIOS的盟主,其BIOS穩定特性廣受各NOTEBOOK大廠所喜好,其缺點是價格較高,授權金額也高.附帶一提,PhoenixTechnology 於1998年遭到Award所併購,但依舊保有其品牌來行銷。,BIOS POST的簡易流程,Boot Block,Start,Decompress,Runtime,Modules,Give Control,to Runtime,Modules,Runtime,Start,Decompress,POST,Modules,POST,Start,Press,Finish the,POST,Decompress,Setup,Modules,Run Setup,YES,NO,BIOS与CMOS區別,常常有人會把BIOS与CMOS當成是一個概念，其實兩者之間是有本質的區別。,CMOS原指一種IC的制程，用CMOS制作的IC具有省電和低溫的特性。用來存儲計算機的設置和系統時期時間。RTC/CMOS RAM整合在南橋中，通過外部搭配的電池供電。因為CMOS制作的內存耗電很低，就算計算机一兩年都不開電源，CMOS中記錄的值也一樣可以得到完整的保存。,BIOS內其實是一些程式，它可以對主机板上所有設備進行測試和參數設定，其參數值存放在CMOS RAM中，BIOS的設置程式可以對CMOS RAM中的值進行修改。,BIOS POST CODE的定義,為了讓設計者和維修者知道BIOS當前在作那些動作，BIOS在檢測和初始化芯片組之前會先丟一個代碼到I/O 80端口，這個代碼我們稱之為Post Code。,我們可以使用80卡透過PCI，ISA和LPC总綫去讀I/O 80端口的代碼，然後顯示LED燈上，這樣便于我們對主机板進行測試和診斷。,由于BIOS生產產商的不同，其代碼也不一樣，我們現以AMI和AWARD這兩個厰商的POST CODE來介紹。,AWARD BIOS POST CODE,C0 ,CPU initialization,Chipsets initialization,Super I/O initialization,Asus ASIC initialization,OEM components initialization,Jumperless Setting,AWARD BIOS POST CODE,C1 ,Memory sizing and initialization,Onboard VGA configuration,0C ,Decompress BIOS codes,C3 ,BIOS checksum,AWARD BIOS POST CODE,After C3,If checksum errors was found, then jump into boot block. Post code would be 05, 0D, 41, 0FF to boot system into DOS mode.,C5 ,Decompress ACPI related codes,AWARD BIOS POST CODE,05 ,Keyboard initialization,07 ,Check RTC power status,09 ,Chipsets registers setting,CPU MSR setting,APIC initialization,AWARD BIOS POST CODE,0A ,BIOS interrupt routines initialization,0B ,CPU information collection,Power management initialization,CMOS contents into memory,PnP early initialization and PCI enumeration,Hardware monitoring initialization,AWARD BIOS POST CODE,0C ,CPU Microcode update,0D ,CPU MTRR setting,VGA initialization,0E ,Showing POST screen,AWARD BIOS POST CODE,18 ,8259 Timer initialization and test,30 ,Memory scanning,31 ,Chassis intrusion detect,Memory rolling test,USB legacy support initialization,AWARD BIOS POST CODE,32 ,PNP device configuration,Super I/O configuration,3D ,Setup ACPI data,PNP Device initialization,Keyboard and Mouse installation,3E ,Hardware monitoring status report,AWARD BIOS POST CODE,41 ,Setup menu entering check,Floppy initialization,42 ,Chipaway Virus initialization,HDD initialization,45 ,Co-processor initialization,4E ,POST error report,Final check with Setup menu entering,4F ,APM initialization,AWARD BIOS POST CODE,AWARD BIOS POST CODE,50 ,Saving all setup menu items settings into CMOS,52 ,PCI devices ROM initialization,Revise interrupt routines hooks,60 ,Mouse RAM reservation,AWARD BIOS POST CODE,61 ,Onboard components final initialization,Showing system configuration,62 ,Keyboard related setting,RTC final check,63 ,PNP final initialization,ESCD, Boot devices, etc.,Boot menu,Jumping into final boot sequence,FF ,Booting into OS,AWARD BIOS POST CODE,AMI BIOS POST CODE,Bootblock Initialization Code Checkpoints,The Bootblock initialization code sets up the chipset, memory and other components before system memory is available. The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the BIOS:,Before D1 -,Early chipset initialization is done. Early super I/O initialization is done including RTC and keyboard controller. NMI is disabled.,D1 -,Perform keyboard controller BAT test. Check if waking up from power management suspend state. Save power-on CPUID value in scratch CMOS.,AMI BIOS POST CODE,D0 -,Go to flat mode with 4GB limit and GA20 enabled. Verify the bootblock checksum.,D2 -,Disable CACHE before memory detection. Execute full memory sizing module. Verify that mode is enabled.,D3 -,If memory sizing module not executed, start memory refresh and do memory sizing in Bootblock code. Do additional chipset initialization. Re_enable CACHE. Verify that flat mode is enabled.,D4 -,Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.,AMI BIOS POST CODE,D5 -,Bootblock code is copied from ROM to lower system memory and control is given to it . BIOS now executes out of RAM.,D6 -,Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced. Main BIOS checksum is tested. If BIOS recovery is necessary, control flows to checkpoint E0. See,Bootblock Recovery Code Checkpoints,section of document for more information.,D7 -,Restore CPUID value back into register. The Bootblock Runtime interface module is moved to system memory and control is given to it. Determine whether to execute serial flash.,AMI BIOS POST CODE,D8 -,The Runtime module is uncompressed into memory. CPUID information is stored in memory.,D9 -,Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory. Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but closing SMRAM.,DA -,Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel). See,POST Code Checkpoints section,of document for more information.,AMI BIOS POST CODE,Bootblock Recovery Code Checkpoints,The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt. The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS:,E0 -,Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled.,E9 -,Set up floppy controller and data. Attempt to read from floppy.,EA -,Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM.,AMI BIOS POST CODE,EB -,Disable ATAPI hardware. Jump back to checkpoint E9.,EF -,Read error occurred on media. Jump back to checkpoint EB.,E9 or EA -,Determine information about root directory of recovery media.,F0 -,Search for pre-defined recovery in root directory.,F1 -,Recovery found.,F2 -,Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file.,AMI BIOS POST CODE,F3 -,Start reading the recovery by cluster.,F5 -,Disable L1 cache.,FA -,Check the validity of the recovery to the current configuration of the flash part.,FB -,Make flash write enabled through chipset and OEM specific method. Detect proper flash part. Verify that the found flash part size equals the recovery .,F4 -,The recovery does not equal the found flash part size.,AMI BIOS POST CODE,FC -,Erase the flash part.,FD -,Program the flash part.,FF -,The flash has been updated successfully. Make flash write disabled. Disable ATAPI hardware. Restore CUPID value back into register. Give control to F000 ROM at F000:FFF0h.,AMI BIOS POST CODE,POST Code Checkpoints,The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. The following table describes the type of checkpoints that may occur during the POST portion of the BIOS:,03 -,Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the Kernel Variable “wCMOSFlags.”,04 -,Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad. Update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system.,AMI BIOS POST CODE,05 -,Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table.,06 -,Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSRINT1CH handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1CH vector to “POSTINT1ChHandlerBlock.”,08 -,Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after Auto detection of KB/MS using AMI KB-5.,C0 -,Early CPU Init Start Disable Cache Init Local APIC.,AMI BIOS POST CODE,C1 -,Set up boot strap processor Information.,C2 -,Set up boot strap processor for POST.,C5 -,Enumerate and set up application processors.,C6 -,Re-enable cache for boot strap processor.,C7 -,Early CPU Init Exit.,0A -,Initializes the 8042 compatible Key Board Controller.,AMI BIOS POST CODE,0B -,Detects the presence of PS/2 mouse.,0C -,Detects the presence of Keyboard in KBC port.,0E -,Testing and initialization of different Input Devices. Also, update the Kernel Variables.,Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and Silent logo modules.,13 -,Early POST initialization of chipset registers.,24 -,Uncompress and initialize and platform specific BIOS modules.,AMI BIOS POST CODE,30 -,Initialize System Management Interrupt.,2A -,Initializes different devices through DIM.,See DIM Code Checkpoint section of document for more information.,2C -,Initializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs.,2E -,Initializes all output devices.,31 -,Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM Module.,AMI BIOS POST CODE,33 -,Initializes the silent boot module. Set the window for displaying test information.,37 -,Displaying sign-on message, CPU information, setup key message, and any OEM specific information.,38 -,Initializes different devices through DIM. See,DIM Code Checkpoints section,of document for more information.,39 -,Initializes DMAC-1 &DMAC-2.,3A -,Initialize RTC date/time.,AMI BIOS POST CODE,3B -,Test for total memory installed in the system. Also, check for DEL or ESC keys to limit memory test. Display total memory in the system.,3C -,Mid POST initialization of chipset registers.,40 -,Detect different devices (Parallel ports, serial ports and coprocessor in CPU, etc.) successfully installed in the system and update the BDA, EBDA etc.,50 -,Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed.,AMI BIOS POST CODE,52 -,Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory.,60 -,Initializes NUM-LOCK status and program the KBD typematic rate.,75 -,Initialize Int-13 and prepare for IPL detection.,78 -,Initializes IPL devices controlled by BIOS and option ROMs.,7A -,Initializes remaining option ROMs.,AMI BIOS POST CODE,7C -,Generate and write contents of ESCD in NVRam.,84 -,Log errors encountered during POST.,85 -,Display errors to the user and get the user response for error.,87 -,Execute BIOS setup if needed /requested.,8C -,Late POST initialization of chipset registers.,8D -,Build ACPI tables (if ACPI is supported),AMI BIOS POST CODE,8E -,Program the peripheral parameters. Enable/Disable NMI as selected,90 -,Late POST initialization of system management interrupt.,A0 -,Check boot password if installed.,A1 -,Clean-up work needed before booting to OS.,A2 -,Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed.,AMI BIOS POST CODE,A4 -,Initialize runtime language module.,A7 -,Displays the system configuration screen if enabled. Initialize the CPUs before boot, which includes the programming of the MTRRs.,A8 -,Prepare CPU for OS boot including final MTRR values.,A9 -,Wait for user input at configures display if needed.,AMI BIOS POST CODE,AA -,Uninstall POST INT1Ch vector and INT09h vector. De-initializes the DMA module.,AB -,Prepare BBS for INT 19h boot.,AC -,End of POST initialization of chipset registers.,B1 -,Save system context for ACPI.,00 -,Passes control to OS Loader (typically INT19h).,AMI BIOS POST CODE,DIM Code Checkpoints,The Device Initialization Manager module gets control at various times during BIOS POST to initialize different Buses. The following table describes the main checkpoints where the DIM module is accessed:,2A -,Initialize different buses and perform the following functions: Reset, Detect, and Disable (function 0); Static Device Initialization (function 1); Boot Output Device Initialization (function 2). Function 0 disables all device nodes, PCI devices, and PNP ISA cards. It also assigns PCI bus numbers. Function 1 initializes all static devices that include manual configured onboard peripherals, memory and I/O decode windows in PCI-PCI bridges, and noncompliant PCI devices. Static resources are also reserved. Function 2 searches for and initializes any PnP, PCI, or AGP video devices.,AMI BIOS POST CODE,38 -,Initialize different buses and perform the following functions: Boot Input Device Initialization (function 3); IPL Device Initialization (function 4); General Device Initialization (function 5). Function 3 searches for and configures PCI input devices and detects if system has standard keyboard controller. Function 4 searches for and configures all PnP and PCI boot devices. Function 5 configures all onboard peripherals that are set to an automatic configuration and configures all remaining PnP and PCI devices.,While control is in the different functions, additional checkpoints are output to port 80h as a word value to identify the routines under execution. The low byte value indicates the main POST Code Checkpoint. The high byte is divided into two nibbles and contains two fields. The details of the high byte of these Checkpoints are as follows:,AMI BIOS POST CODE,HIGH BYTE XY,The upper nibble X indicates the function number that is being executed. X can be from 0 to 7 .,0 = func#0, disable all devices on the BUS concerned.,1 = func#1, static devices initialization on the BUS concerned.,2 = func#2, output device initialization on the BUS concerned.,3 = func#3, input device initialization on the BUS concerned.,4 = func#4, IPL device initialization on the BUS concerned.,5 = func#5, general device initialization on the BUS concerned.,6 = func#6, error reporting for the BUS concerned.,7 = func#7, add-on ROM initialization for all Buses.,8 = func#8, BBS ROM initialization for all Buses.,AMI BIOS POST CODE,The lower nibble Y indicates the BUS on which the different routines are being executed. Y can be from 0 to 5.,0 = Generic DIM (Device Initialization Manager).,1 = On-board System devices.,2 = ISA Devices.,3 = EISA Devices.,4 = ISA PnP devices.,5 = PCI devices.,AMI BIOS POST CODE,ACPI Runtime Checkpoints,ACPI checkpoints are displayed when an ACPI capable operating system either enters or leaves a sleep state. The following table describes the type of checkpoints that may occur during ACPI sleep or wake events:,AC -,First ASL check point. Indicates the system is running in ACPI mode.,AA -,System is running in APIC mode.,01,02,03,04,05 -,Entering sleep state S1, S2, S3, S4 or S5.,10,20,30,40,50 -,Waking from sleep state S1, S2, S3, S4 or S5.,