LVDS与TMDS得比较

Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,*,*,L,D,I,LVDS,N,A comparison of,LVDS vs. TMDS,for LCD Monitor Applications,February 1999,Interface Applications,9/13/2024,1,LDI,LVDS Display Interface,(Low Voltage Differential Signaling)offered by,National Semiconductor Corp,.,PanelLink / TMDS ,Transition Minimized Differential Signalingoffered by Silicon Image Inc.,9/13/2024,2,Goals of a Monitor Interface,Supports a wide range of panels,Drive long, low cost cables,Low EMI,High noise rejection,Open Standard,Multiple sources (ICs, Cables, Connectors),Low Cost,9/13/2024,3,LDI Block Diagram,RED 1,GRN 1,BLUE 1,FPLINE,FPFRAME,FPSHIFT IN,32.5 - 112 MHz,(170 MHz SPM),DRDY,Control,CMOS/TTL Inputs,LVDS CLOCK,(32.5 to 112 MHz),LVDS,DATA,DS90C387,RED 2,GRN 2,BLUE 2,DC BALANCE,PLL,DS90CF388,DC BALANCE DECODE & DESKEW,PLL,RED 1,GRN 1,BLUE 1,FPLINE,FPFRAME,FPSHIFT OUT,32.5 - 112 MHz,DRDY,RED 2,GRN 2,BLUE 2,CMOS/TTL Inputs,TTL PARALLEL - TO - LVDS,8,8,8,8,8,8,5.376 Gbps,LVDS - TO - TTL PARALLEL,8,8,8,8,8,8,Control,9/13/2024,4,TMDS Block Diagram,RED 1,GRN 1,BLUE 1,Control,DE,TIC,25 - 112MHz,Control,CMOS/TTL Inputs,TMDS CLOCK,(25 to 112MHz),TMDS,DATA,SiI1x0,RED 2,GRN 2,BLUE 2,Data Capture,SERIALIZER,8,8,8,8,8,8,PLL,SiI1x1,TMDS DECODER,PLL,RED 1,GRN 1,BLUE 1,Control,DE,CLOCK,25 - 112MHz,RED 2,GRN 2,BLUE 2,8,8,8,8,8,8,CMOS/TTL Inputs,2.68 Gbps,TMDE DC-Balanced ENCODER,BUFFER,DE-SERIALIZER,5,5,9/13/2024,5,Panel I/F Bandwidth Demands,Panel,XGA,SXGA,SXGAW,UXGA,HDTV,UXGAW,Resolution,1024 X 768,1280 X 1024,1600 X 1024,1600 X 1200,1920 X1080,1900 X 1200,QXGA,2048 X 1536,CLK,(MHz),65,93,115,133,143,158,211,RGB,8,8,8,8,8,8,8,Bandwidth,(Gbps),1.56,2.23,2.76,3.29,3.43,3.79,5.06, 60 Hz refresh / reduced blanking,5,Gbps is the need!,9/13/2024,6,The OpenLDI Advantage!,Bandwidth for todays (SXGA) and tomorrows (UXGA/HDTV/QXGA) high-resolution displays,Open Standard:,Physical layer defined in ANSI/TIA/EIA-644,Low cost, multiple suppliers of cable & connectors,Multiple suppliers of LVDS silicon today,No Licenses required,Compatible with todays de-facto Notebook standard digital interface (FPD-Link),9/13/2024,7,LDI vs. TMDS,LDI,TMDS,Architecture,7X,10X,Data Pairs,8 (or 4),3,Clock Pairs,1,1,Encoding,NO,YES,DC Balance,YES,YES,LVDS Standard,YES,NO,# of Shields in cable,1,5,Pre-emphasis,YES,NO,Deskew (pair-pair),1bit,1bit,1,Intra-pair Skew (+ to -),300ps,5%tbit,2,Note 1: Per VESA P&D Standard, deskew is +/- 1bit time, PanelLink can deskew pair-to-pair skew up to 1 clock cycle.,Note 2: Per VESA P&D Standard, Intra-pair skew is 5% maximum of a bit time, SiI datasheet states 10% maximum.,only,31ps,for,UXGA,9/13/2024,8,Architecture Impact - UXGA,Cable Clock Freq. (MHz),162 MHz,81 MHz,Channel Speed (bps),1.62 Gbps,567 Mbps,Chipset Throughput (bps),4.860 Gbps,4.536 Gbps,Information Rate (bps),3.888 Gbps,3.888 Gbps,Bit Time (s),617 ps,1.764 ns,LDI,TMDS,Intra-pair Skew (ps),31 or 62ps,300ps,9/13/2024,9,Timing Parameter Comparison,XGA,yesterday,65MHz,SXGA,today,112MHz,UXGA,tomorrow,162MHz,HDTV,soon,143MHz,QXGA,future,211MHz,0.650,1.950,1.538,1.120,3.360,0.892,1.621,4.860,0.617,1.430,4.290,0.699,2.110,6.330,0.474,0.227,1.820,4.396,0.392,3.136,2.551,0.567,4.536,1.764,0.500,4.004,1.998,0.738,5.908,1.354,LDI supports SVGA to QXGA today!,LDI keeps line speed under 1Gbps,LDI bit time is greater than 1ns,LDI total bandwidth (BW) is lower since more efficient,Panel Specifications,PanelLink,LDI,Panel,Clock,Line Speed,Gbps,Total BW,Gbps,Bit Time,ns,Line Speed,Gbps,Total BW,Gbps,Bit Time,ns,9/13/2024,10,Data Payload Comparison,Bit 0,Bit 1,Bit 2,Bit 3,Bit 4,Bit 5,DC,EN,Bit 0,Bit 1,Bit 2,Bit 3,Bit 4,Bit 5,Bit 6,Bit 7,DC,LDI,7 bits per clock,86% efficient,No Encoding,DC Balanced,TMDS,10 bits per clock,80% efficient,Encoded,DC Balanced,CLK,Data,CLK,Data,CLK Period,9/13/2024,11,7,is,Better,than,10,Bit widths are larger - better cable transmission,Maximum bandwidth is higher - supports higher resolution panels today,Timing margins are larger - better data recovery,Inter-pair skew tolerance is larger (equal to a bit time),Intra-pair skew tolerance is larger (% of a bit time),Lower frequency circuitry on chip:,promotes integration,less high frequency EMI,9/13/2024,12,Efficiency Comparison,LDI,7 bit payload,6 Pixel Data bits,1 DC Balance Bit,TMDS,10 bit (TM Encoded) payload,8 Pixel Data bits,1 encoding bit,1 DC Balance bit,86%,80%,LVDS,6,7,8,10,9/13/2024,13,LDI Transmission,Pixel Data,7 bit frame (6 data),DC Balanced,86% Efficient,Divide by 7:,Larger sub symbols,Maximizes Sampling Margins,Increases Intra-pair skew tolerance,Control Data,Minimum Transitions (2 maximum),Active Data,Blanking,DE,9/13/2024,14,TMDS Transmission,Pixel Data,10 bit frame (8 data),DC Balanced,Encoded (22% less transitions),80% Efficient,Divide by 10:,decreases F maximum,decreases intra-pair skew tolerance,Control Data,Maximum Transitions (8 transitions per pair),DC Balanced,Active Data,Blanking,DE,Transition Minimized,T Maximized,9/13/2024,15,SXGA ApplicationTransition Comparison,ACTIVE,DATA,72.5%,BLANKING,27.5%,3.5 transitions,X 4 Pairs =,14,2 transitions,X 4 Pairs =,8,3.12* transitions,X 3 Pairs =,9.36,8 transitions,X 3 Pairs =,24,TOTAL,(100%),12.35,13.39,SXGA application w/ 112 MHz, 60Hz refresh:,LDI in,Single Pixel Mode,(4 Data Pairs + Clock),PanelLink (3 Data Pairs + Clock), *3.12 = 4-22%,LDI,TMDS,L,D,I,LVDS,9/13/2024,16,Transition Comparison,Open LDI has,LESS,transitions than TMDS!,LDI minimizes transitions during blanking,LDI has no encoding overhead,TMDS only “minimizes” transitions during active data,TMDS,maximizes,transitions during blanking,9/13/2024,17,Data Bit Width vs. Frequency,5Gbps),Long, Low Cost Cables,Compatible with Notebooks,Open Standard - No Licenses,LDI,Yes,Yes,Yes,Yes,TMDS,No,No,No,No,9/13/2024,32,