Copyright2001,Agrawal&Bushnell

Click to edit Master title style,Click to edit Master text styles,Second Level,Third Level,Fourth Level,Fifth Level,Copyright 2001, Agrawal & Bushnell,*,Click to edit Master title style,Click to edit Master text styles,Second Level,Third Level,Fourth Level,Fifth Level,Copyright 2001, Agrawal & Bushnell,*,VLSI Testing,Lecture 2: Yield & Quality,Yield and manufacturing cost,Clustered defect yield formula,Defect level,Test data analysis,Example: SEMATECH chip,Summary,Problems to solve,VLSI Chip Yield,A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process.,A chip with no manufacturing defect is called a good chip.,Fraction (or percentage) of good chips produced in a manufacturing process is called the,yield,. Yield is denoted by symbol,Y,.,Cost of a chip:,Cost of fabricating and testing a wafer,Yield x Number of chip sites on the wafer,Clustered VLSI Defects,Wafer,Defects,Faulty chips,Good chips,Unclustered defects,Wafer yield = 12/22 = 0.55,Clustered defects (VLSI),Wafer yield = 17/22 = 0.77,Yield Parameters,Defect density (,d,) = Average number of defects per unit of chip area,Chip area (,A,),Clustering parameter (,),Negative binomial distribution of defects,p,(,x,) = Prob (number of defects on a chip =,x,),G,(,a,+,x,) (,Ad,/,a,),x,= - . -,x,!,G,(,a,) (1+,Ad,/,a,),a,+,x,where,is the gamma function,a,= 0,p,(,x,),is a delta function (maximum clustering),a,=,p,(,x,),is Poisson distribution (no clustering),Yield Equation,Y,= Prob ( zero defect on a chip ) =,p,(0),Y,= ( 1 +,Ad,/,a,),- a,Example:,Ad,= 1.0,= 0.5,Y,= 0.58,Unclustered defects:,=,Y,= e,-,Ad,Example,:,Ad,= 1.0,=,Y,= 0.37,too pessimistic,!,Defect Level or Reject Ratio,Defect level,(,DL,) is the ratio of faulty chips among the chips that pass tests.,DL,is measured as,parts per million,(ppm).,DL,is a measure of the effectiveness of tests.,DL,is a quantitative measure of the manufactured product quality. For commercial VLSI chips a,DL,greater than 500 ppm is considered unacceptable.,Determination of DL,From field return data: Chips failing in the field are returned to the manufacturer. The number of returned chips normalized to one million chips shipped is the,DL,.,From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the,DL,.,Modified Yield Equation,Three parameters:,Fault density,f,= average number of stuck-at faults per unit chip area,Fault clustering parameter,Stuck-at fault coverage,T,The modified yield equation:,Y,(,T,) = (1 +,TAf,/,b,),-,b,Assuming that tests with 100% fault coverage,(,T,=1.0,) remove all faulty chips,Y = Y,(1) = (1 +,Af,/,b,),-,b,Defect Level,Y,(,T,) -,Y,(1),DL,(,T,) =,Y,(,T,),(,b,+,TAf,),b,= 1 ,(,b,+,Af,),b,Where,T,is the fault coverage of tests,Af,is the average number of faults on the chip of area,A,is the fault clustering parameter.,Af,and,are determined by test data analysis.,Example: SEMATECH Chip,Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont,116,000 equivalent (2-input NAND) gates,304-pin package, 249 I/O,Clock: 40MHz, some parts 50MHz,0.8m CMOS, 3.3V, 9.4mm x 8.8mm area,Full scan, 99.79% fault coverage,Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock,Data obtained courtesy of Phil Nigh (IBM),Test Coverage from Fault Simulator,Stuck-at fault coverage,Vector number,Measured Chip Fallout,Vector number,Measured chip fallout,Model Fitting,Y,(,T,) for,Af,= 2.1 and,b,= 0.083,Measured chip fallout,Y,(1) = 0.7623,Chip fallout and computed 1 -,Y,(,T,),Stuck-at fault coverage,T,Chip fallout vs. fault coverage,Computed DL,Stuck-at fault coverage (%),Defect level in ppm,237,700 ppm (,Y,= 76.23%),Summary,VLSI yield depends on two process parameters, defect density (,d,),and clustering parameter (,).,Yield drops as chip area increases; low yield means high cost.,Fault coverage measures the test quality.,Defect level (,DL,) or reject ratio is a measure of chip quality.,DL,can be determined by an analysis of test data.,For high quality:,DL 500 ppm, fault coverage 99%,Problems to Solve,Using the expression for defect level on Slide 9, derive test coverage (T) as a function of fault clustering parameter (,), defect level (DL), and average number of faults (Af) on a chip.,Find the defect level for:,Fault density, f = 1.45 faults/sq. cm,Fault clustering parameter,= 0.11,Chip area = 1 cm,2,Fault Coverage, T = 95%,Solution 1,Defect level, DL, is given on Slide 9, as follows:,DL = 1 (, + Taf)/( + Af),where T is the fault coverage, Af is the average number of faults on a chip of area A, and, is a fault clustering parameter. Further manipulation of this equation leads to the following result:,(1 DL),1/,= (, + Taf)/( + Af),or T = ,(,+ Af)(1 DL),1/,/(Af),100 percent,Solution 2,Defect level, DL, as given on Slide 9, is:,DL(T) = 1 (, + Taf)/( + Af),Substituting,Fault density, f = 1.45 faults/sq. cm,Fault clustering parameter,= 0.11,Chip area = 1 cm,2,Fault Coverage, T = 95%,We get,DL(T) = 0.00522 or 5,220 parts per million,