SCISerialCommunicationsInterface

Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,*,*,SCI: Serial Communications Interface,Presented by:,Sean Kline,Chad Smith,Jamie Cruce,1,Outline,General Description of the SCI,Serial vs. Parallel Transmission,Synchronous vs. Asynchronous Transmission,Start, Stop, Data, and Parity Bits,Baud vs. Bit Rate,Noise,SCI Registers,Data Word Transmission Examples,2,What is it?,An independent serial I/O system used with the M68HC11 microcontroller,Universal Asynchronous Receiver Transmitter,(UART),3,Serial vs. Parallel,Serial,Data transmitted in one line,Slower than parallel transmission,Parallel,Data transmitted in multiple lines,Requires one line per bit of data transmitted in a concurrent fashion,Faster than serial transmission,4,Synchronous vs. Asynchronous,Synchronous,One-way communication,Receiver and transmitter must have their clocking “synchronized,” requiring a constant stream of transmission,Request for data is made, time is given for the request to be carried out, and data is read.,Asynchronous,Utilizes start and stop bit to communicate the beginning and end of data words to the receiver,No need for devices to be synchronized,5,Data Word,Start Bit,Signals the start of transmission of the data bits,Transition from logic 1 to logic 0,Data Bits,Generally 8 data bits (not including parity bit),Transmitted and received least significant bit first,Stop Bit,Signals the end of a data word,Logic 1,6,Parity Bit,Can be added to the transmitted data to check for and display an error message when a bit is lost during transmission,Comes in two forms,Odd Parity,Sum of the 1s in the frame will be odd,The logical state (1 or 0) of the parity bit is selected to fulfill this condition,Even Parity,Sum of the 1s in a frame will be even,Number of 1s checked against the parity bit to determine if any bits were lost during transmission,A two bit loss will go undetected with this method,7,Data Word,8,Baud and Bit Rates,Baud Rate,A baud is the “reciprocal of the shortest pulse duration in a data word” inclusive of start, stop, data, and parity bits,Baud rate is the,total,number of bits transmitted per second,Data Bit Rate,The number of,data,bits transmitted in one second.,Does,not,include the start or stop bits,9,In this example:,1 start bit, 1 stop bit, 1 parity bit, 8 data bits, 11 bits per word, 300 baud rate,Bit Time = 1/(Baud rate) = 1/300 = 3.33 msec,Character Time = (total bits in word) x (bit time) = 11 x 3.33 = 36.6 msec,Data Bit Rate (including parity) = (data bits in word)/(character time)= 9/3.33 = 270,10,Noise,Noise will cause interference in the line, which might cause the word to be misinterpreted,Three samples will be taken near the middle of the bit time,If noise is detected the noise flag will be set, but the bit will be accepted if there are more non-noise samples than noise (majority rules),When the start bit is detected, four additional samples are taken during the first half of the time bit to verify the start bit,11,Noise,Noise can cause the start bit to be detected too soon,Noise flag will be set since RT3 is 1,Start bit will be accepted because majority of samples are 0,12,SCI Registers,BAUD sets bit rate,SCCR1 (Control Register 1) contains control bits related to the 9-bit data character format and the receiver wake-up feature,SCCR2 (Control Register 2) main control register for the SCI subsystem,SCSR (Status Register) generate hardware interrupt requests and indicate errors in the reception of a character,SCDR (Data Register) main data register for transmitting and receiving (contains a buffer),13,BAUD Register,TCLR clear baud rate timing chain bit (factory testing of MCU),SCP1-SCP0 baud rate prescale select bits (determines highest available baud rate in system),RCKB baud rate clock test bit (factory testing of MCU),SCR2-SCR0 baud rate select bits (selects an additional binary submultiple of the highest baud rate),Bits are determined based on the baud rates found in Table 9-3 of HC11 Reference Manuel,Address: $102B,Read:,Write:,Reset:,Bit 7 6 5 4 3 2 1 0,0 0 0 0 0 U U U,0,TCLR,SCP1,SCP0,SCR2,SCR0,SCR1,0,0,RCKB,14,SCCR1 Register,Address: $102C,Read:,Write:,Reset:,Bit 7 6 5 4 3 2 1 0,U U 0 0 0 0 0 0,R8,T8,0,M,WAKE,0,0,0,R8 receive data bit 8 (acts as extra bit of RDR),T8 transmit data bit 8 (acts as extra bit of the TDR),M SCI character length bit (controls the character length for both transmitter and receiver at same time),WAKE wakeup method select bit,Idle line detection of at least a full character time of idle line,Address mark a logic 1 in MSB,15,SCCR2 Register,Address: $102D,Read:,Write:,Reset:,Bit 7 6 5 4 3 2 1 0,0 0 0 0 0 0 0 0,TIE,TCIE,RIE,ILIE,TE,RE,RWU,SBK,TIE transmit interrupt enable bit,TCIE transmit complete interrupt enable bit,RIE receive interrupt enable bit,ILIE idle-line interrupt enable bit,TE transmit enable bit,RE receive enable bit,RWU receiver wakeup bit,SBK send break bit,16,SCSR Register,Address: $102E,Read:,Write:,Reset:,Bit 7 6 5 4 3 2 1 0,1 1 0 0 0 0 0 0,TDRE,TC,RDRF,IDLE,OR,NF,FE,0,TDRE transmit data register empty bit (see if SCDR can accept new data),TC transmit complete bit,RDRF receive data register full bit,IDLE idle-line detect bit (full character time of logic 1 on the RxD line),OR overrun error bit (received character was not read before new character was sent),NF noise Flag,FE framing error bit (logic 0 is detected where stop bit was expected),17,SCDR Register,Address: $102F,Read:,Write:,Reset:,Bit 7 6 5 4 3 2 1 0,U U U U U U U U,R7,R6,R5,R4,R3,R2,R1,R0,T7,T6,T5,T4,T3,T2,T1,T0,When SCDR is read , the read-only RDR is accessed,When SCDR is written, the write-only TDR is accessed,18,Port D Related Registers,PORTD,SCI uses the two LSBs for input/output,DDRD data direction register for port D,Is not used while SCI is in use but will take over control of port D when the SCI operation is aborted,19,Steps for Transmitting Data,Set Baud rate ($102B) to equal receiver,Set TE in SCCR2 ($102B) high to enable,Set Wake Up mode in SCCR1 ($102C),TE sends idle character to wake receiver,Receiver determines if message is intended for it,Load character into SCDR ($102F),Character placed in shift register and shifted out,When TDRE in SCSR ($102E) sets back to 1, load another character (both polling and interrupts can be used),Transmission complete (TC in SCSR),Idle line rests at logic 1, RWU goes to 0,20,Steps for Receiving Data,Set Baud rate in Baud register ($102B),Set bit 4 in SCCR1 ($102C) to select 8 or 9 bit characters; set bit 3 to select wake up mode,Set bit 2 in SCCR2 ($102D) to enable receiver; set bit 4 to enable interrupt on idle; set bit 5 to enable interrupt when character received or overrun occurs,Read status of receive from SCSR ($102E) Bit 5 will be set when data is received; framing error sets bit 1; noise sets bit 2; overrun sets bit 3; idle sets bit 4,Read data received from SCDR ($102F),If 9 bit data format is used, the ninth bit of data will be located in bit 7 of SCCR1 ($102C),21,Example for Transmitting Data,*-* Test program for transmitting for serial data. User* specifies 8-bit data. See below.*-MAIN EQU $1040 *Assemble code here starting at $1040PORTC EQU $1003 *Equate PORTC to $1003DDRC EQU $1007 *Equate data direction register DDRCSCCR2 EQU $102D *Equate SCI control register 2BAUD EQU $102B *Equate BAUD registerSCSR EQU $102E *Equate SCI status registerSCDR EQU $102F *Equate SCI data register*=PROGRAM= ORG MAIN LDAA #$33 *Select 1200 baud. Refer to Pink book P9-7 STAA BAUD LDAA #$08 *Enable TE STAA SCCR2LOOP LDAA #$8B *Put data into TXD for transmission. User *specify data here! STAA SCDR *Put transmit data into SCI data registerCHECK LDAA SCSR *Check to see if data has been transferred ANDA #$C0 CMPA #$C0 BNE CHECK BRA LOOP *Do it again,22,References,“M68HC11E Family Data Sheet”,pages 117-131,Basic Microprocessors and the 6800,by Ron Bishop, pages 184-199,“M68HC11E Reference Manual”,pages 318-365,23,Questions,24,