Counters-and-Shift-Registers计数器与移位寄存器教学课件

316 317Bi-SRPL-SRshift_leftshift_right318 00011011319 sht_rightsht_leftpar_load320 VHDLv Structured VHDL Design VHDL.LSR,RSR DFF primitive.DFF Primitive Port Map D,CLK,Q.v DataFlow Design VHDL .Entity .Qi Buffer.v Behavioral design VHDL .321Structured VHDL I(BUFFER)322Structured VHDL II(signal)323Dataflow VHDLconcurrent324Behavioral VHDL325Ex.9.15 Bidir.SRG VHDL326Ex.9.15 Bidir.SRG Simulation327Generic Width Shift Register VHDL Generic(clause).Width ,Generic .GENERIC(Clause:=Value).4-Bit ,GENERIC(Width:Positive:=4).328GENERIC 4-bit Shit Right 329GENERIC 8-bit Shit Right(4-bit SRG)3308-bit Universal SRGCONV_STD_LOGIC_VECTOR(value,number_of_bits)q 0);-q=00000000;-aggregateq 0);-q=0100000033116-bit Universal SRG(8-bit universal SRG)332LPM lpm_shiftreg LPM .LPM_WIDTH,LPM_DIRECTION .(9.16)VHDL .3338-bit LPM SRG(Shift left)3348-bit LPM (Shift left)Buried nodes3358-bit LPM SRG(Shift right)3368-bit LPM (Shift Right)3378-bit LPM SRG(shift left,pl,aclr)sq_out(7)serial_out 3388-bit LPM SRG Simulation(shift left,pl,aclr)AA339 (Ring Counters)D-FF.“1000”“0111”1 0.:1000,0100,0010,0001=Mod4,1010,0101=Mod2.N N-.(2N .)().340 Q0 !Q0(Complement)D3 .“twist”“Twisted Ring Counter”.“0000”.=0000,1000,1100,1110,1111,0111,0011,0001.N-2N.2-input AND(or NAND).(9.18&9.19).(Johnson Counters)3414-bit Johnson counter with a synchronous clear3428-bit Johnson counter with a synchronous clear3438-bit 344Summaryv Counter behavioral description LPM Structural description .v Behavioral counter design process .if /.(clkEVENT and clk=1)v Variable:=.v process sensitivity list .v process sensitivity list .v VHDL component parameter .parameter component entity GENERIC .345