VerilogHDL简易时钟的层次化设计程序代码

VerilogHDL简易时钟的层次化设计程序代码module top(clk0,clk1,q,s);input clk1,clk0;output7:0 q;/reg7:0 q;output2:0s;/reg2:0s;wire23:0 w;cnt60 m0(clk1,w7:0,cp0);/秒计数模块cnt60 m1(cp0,w15:8,cp1);/分计数模块cnt24 m2(w23:16,cp1);/时计数模块wx m3(clk0,clk1,c,s,w3:0,w11:8,q,w19:16,w6:4,w14:12,w21:20); endmodulemodule wx(clk0,clk1,c,s,c0,c3,q,c6,c1,c4,c7);input clk0,clk1;input3:0 c0,c3;input2:0 c1,c4;input3:0 c6;input1:0c7;output7:0q;reg7:0q;output 2:0s;output 3:0c;reg 3:0c;reg 2:0s1,s;/位选always(posedge clk0) beginif(s13b111)s1=s1+1b1;else s1=3b000;case(s1)3b000:begin s=3b000;c=c0;end3b001:begin s=3b001;c=c1;end3b011:begin s=3b011;c=c3;end3b100:begin s=3b100;c=c4;end3b110:begin s=3b110;c=c6;end3b111:begin s=3b111;c=c7;end default begin s=3b000;c=c0;end endcaseend/always(posedge clk1)(有误，不要)always(c)case(c)4b0000:q=8b00111111;4b0001:q=8b00000110;4b0010:q=8b01011011;4b0011:q=8b01001111;4b0100:q=8b01100110;4b0101:q=8b01101101;4b0110:q=8b01111101;4b0111:q=8b00000111;4b1000:q=8b01111111;4b1001:q=8b01101111;default q=8b00111111;endcaseendmodule/60 计数module cnt60(clk,qs,co);input clk;output 7:0 qs;output co;reg7:0 qs;reg co;always(posedge clk)beginif(qs7:4!=5)beginbeginif(qs3:0=4b1001)qs7:4=qs7:4+1b1;qs3:0=4b0000;co=1b0;end else begin qs7:4=qs7:4;qs3:0=qs3:0+1b1;co=1b0;endendelseif(qs3:0=4b1001) begin qs7:4=4b0000;qs3:0=4b0000;co=1b1;endelse begin qs7:4=qs7:4;qs3:0=qs3:0+1b1;co=1b0;endendendmodule/ 24计数(无误)module cnt24(qh,clk);input clk;output 7:0 qh;reg7:0 qh; always(posedge clk)begin if(qh7:4!=2)beginif(qh3:0=4b1001) begin qh7:4=qh7:4+1b1;qh3:0=4b0000;end else begin qh7:4=qh7:4;qh3:0=qh3:0+1b1;end endelseif(qh3:0=4b0011) begin qh7:4=4b0000;qh3:0=4b0000;endelse begin qh7:4=qh7:4;qh3:0=qh3:0+1b1;endendendmodule