51单片机外文文献

The Introduction of AT89C51DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, one 5 vector two-level interrupt architecture, a full duplex serial port, one-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 may also be configured to be the multiplexed address/data bus during accesses to external program and data memory. In this mode P0 has internal Pull-up resistor. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during Program verification. External Pull-up resistors are required during Program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal Pull-up resistors. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal Pull-up resistors and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal Pull-up resistors. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal Pull-up resistor. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal Pull-up resistor and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current, because of the internal Pull-up resistor. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal Pull-up resistor when emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal Pull-up resistor. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal Pull-up resistor and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the Pull-up resistor. Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationIdle ModeIn idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.译文： AT89C51的简介 描述AT89C51是一种低电压，高性能CMOS 8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。这种器件采用ATMEL公司的高密度、不容易丢失存储技术生产，并且可以与MCS-51系列的单片机兼容。片内具有8位中央解决器和闪烁存储单元，有较强的功能的AT89C51单片机可以被应用到控制领域中。功能特性AT89C51提供如下的功能原则：4K字节闪烁存储器，128字节随机存取数据存储器，32个I/O口，2个16位定期/计数器，1个5向量两级中断构造，1个串行通信口，片内震荡器和时钟电路。此外，AT89C51还可以进行0HZ的静态逻辑操作，并支持两种软件的节电模式。闲散方式停止中央解决器的工作，可以容许随机存取数据存储器、定期/计数器、串行通信口及中断系统继续工作。掉电方式保存随机存取数据存储器中的内容，但震荡器停止工作并严禁其他所有部件的工作直到下一种复位。引脚描述VCC：电源电压 GND：地P0口P0口是一组8位漏极开路双向I/O口，即地址/数据总线复用口。作为输出口时，每一种管脚都可以驱动8个TTL电路。当“1”被写入P0口时，每个管脚都可以作为高阻抗输入端。P0口还可以在访问外部数据存储器或程序存储器时，转换地址和数据总线复用，并在这时激活内部的上拉电阻。P0口在闪烁编程时，P0口接受指令，在程序校验时，输出指令，需要接电阻。P1口P1口一种带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动4个TTL电路。对端口写“1”，通过内部的电阻把端口拉到高电平，此时可作为输入口。由于内部有电阻，某个引脚被外部信号拉低时输出一种电流。闪烁编程时和程序校验时，P1口接受低8位地址。P2口P2口是一种内部带有上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动4个TTL电路。对端口写“1”，通过内部的电阻把端口拉到高电平，此时，可作为输入口。由于内部有电阻，某个引脚被外部信号拉低时会输出一种电流。在访问外部程序存储器或16位地址的外部数据存储器时，P2口送出高8位地址数据。在访问8位地址的外部数据存储器时，P2口线上的内容在整个运营期间不变。闪烁编程或校验时，P2口接受高位地址和其他控制信号。P3口P3口是一组带有内部电阻的8位双向I/O口，P3口输出缓冲故可驱动4个TTL电路。对P3口写如“1”时，它们被内部电阻拉到高电平并可作为输入端时，被外部拉低的P3口将用电阻输出电流。P3口除了作为一般的I/O口外，更重要的用途是它的第二功能，如下表所示：端口引脚第二功能P3.0RXDP3.1TXDP3.2INT0P3.3INT1P3.4T0P3.5T1P3.6WRP3.7RDP3口还接受某些用于闪烁存储器编程和程序校验的控制信号。RST复位输入。当震荡器工作时，RET引脚浮现两个机器周期以上的高电平将使单片机复位。ALE/ PROG当访问外部程序存储器或数据存储器时，ALE输出脉冲用于锁存地址的低8位字节。虽然不访问外部存储器，ALE以时钟震荡频率的1/16输出固定的正脉冲信号，因此它可对输出时钟或用于定期目的。要注意的是：每当访问外部数据存储器时将跳过一种ALE脉冲时，闪烁存储器编程时，这个引脚还用于输入编程脉冲。如果必要，可对特殊寄存器区中的8EH单元的D0位置严禁ALE操作。这个位置后只有一条MOVX和MOVC指令ALE才会被应用。此外，这个引脚会单薄拉高，单片机执行外部程序时，应设立ALE无效。PSEN程序储存容许输出是外部程序存储器的读选通信号，当AT89C51由外部程序存储器读取指令时，每个机器周期两次PSEN 有效，即输出两个脉冲。在此期间，当访问外部数据存储器时，这两次有效的PSEN 信号不浮现。EA/VPP外部访问容许。欲使中央解决器仅访问外部程序存储器，EA端必须保持低电平。需要注意的是：如果加密位LBI被编程，复位时内部会锁存EA端状态。如EA端为高电平，CPU则执行内部程序存储器中的指令。闪烁存储器编程时，该引脚加上+12V的编程容许电压VPP，固然这必须是该器件是使用12V编程电压VPP。XTAL1：震荡器反相放大器及内部时钟发生器的输入端。XTAL2：震荡器反相放大器的输出端。时钟震荡器AT89C51中有一种用于构成内部震荡器的高增益反相放大器，引脚XTAL1和XTAL2分别是该放大器的输入端和输出端。这个放大器与作为反馈元件的片外石英晶体或陶瓷谐振器一起构成自然震荡器。 外接石英晶体及电容C1，C2接在放大器的反馈回路中构成并联震荡电路。对外接电容C1，C2虽然没有十分严格的规定，但电容容量的大小会轻微影响震荡频率的高下、震荡器工作的稳定性、起振的难易程序及温度稳定性。如果使用石英晶体，我们推荐电容使用30PF10PF，而如果使用陶瓷振荡器建议选择40PF10PF。顾客也可以采用外部时钟。采用外部时钟的电路如图示。这种状况下，外部时钟脉冲接到XTAL1端，即内部时钟发生器的输入端，XTAL2则悬空。由于外部时钟信号是通过一种2分频触发器后作为内部时钟信号的，因此对外部时钟信号的占空比没有特殊规定，但最小高电平持续时间和最大的低电平持续时间应符合产品技术条件的规定。内部振荡电路外部振荡电路闲散节电模式AT89C51有两种可用软件编程的省电模式，它们是闲散模式和掉电工作模式。这两种方式是控制专用寄存器PCON中的PD和IDL位来实现的。PD是掉电模式，当PD=1时，激活掉电工作模式，单片机进入掉电工作状态。IDL是闲散等待方式，当IDL=1，激活闲散工作状态，单片机进入睡眠状态。如需要同步进入两种工作模式，即PD和IDL同步为1，则先激活掉电模式。在闲散工作模式状态，中央解决器CPU保持睡眠状态，而所有片内的外设仍保持激活状态，这种方式由软件产生。此时，片内随机存取数据存储器和所有特殊功能寄存器的内容保持不变。闲散模式可由任何容许的中断祈求或硬件复位终结。终结闲散工作模式的措施有两种，一是任何一条被容许中断的事件被激活，IDL被硬件清除，即刻终结闲散工作模式。程序会一方面影响中断，进入中断服务程序，执行完中断服务程序，并紧随RETI指令后，下一条要执行的指令就是使单片机进入闲散工作模式，那条指令背面的一条指令。二是通过硬件复位也可将闲散工作模式终结。需要注意的是：当由硬件复位来终结闲散工作模式时，中央解决器CPU一般是从激活空闲模式那条指令的下一条开始继续执行程序的，要完毕内部复位操作，硬件复位脉冲要保持两个机器周期有效，在这种状况下，内部严禁中央解决器CPU访问片内RAM，而容许访问其她端口，为了避免也许对端口产生的意外写入：激活闲散模式的那条指令背面的一条指令不应是一条对端口或外部存储器的写入指令。掉电模式在掉电模式下，振荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内RAM和特殊功能寄存器的内容在中指掉电模式前被冻结。退出掉电模式的唯一措施是硬件复位，复位后将从新定义所有特殊功能寄存器但不变化RAM中的内容，在VCC恢复到正常工作电平前，复位应无效切必须保持一定期间以使振荡器从新启动并稳定工作。闲散和掉电模式外部引脚状态。模式程序存储器ALEP0P1P2P3闲散模式内部11数据数据数据数据闲散模式内部11浮空数据地址数据掉电模式外部00数据数据数据数据掉电模式外部00数据数据数据数据程序存储器的加密AT89C51可使用对芯片上的三个加密位LB1，LB2，LB3进行编程（P）或不编程（U）得到如下表所示的功能：程序加密位保护类型1UUU没有程序保护功能2PUU严禁从外部程序存储器中执行MOVC指令读取内部程序存储器的内容3PPU除上表功能外，还严禁程序校验4PPP除以上功能外，同步严禁外部执行当LB1被编程时，在复位期间，EA端的电平被锁存，如果单片机上电后始终没有复位，锁存起来的初始值是一种不拟定数，这个不拟定数会始终保存到真正复位位置。为了使单片机正常工作，被锁存的EA电平与这个引脚目前辑电平一致。机密位只能通过整片擦除的措施清除。