基于Libero的数字逻辑设计仿真及验证实验报告

_计算机_学院 计算机科学与技术 专业 班、学号 姓名 协作者_ 教师评定_实验题目_基于Libero的数字逻辑设计仿真及验证实验_1、 熟悉EDA工具的使用；仿真基本门电路。2、 仿真组合逻辑电路。3、 仿真时序逻辑电路。4、 基本门电路、组合电路和时序电路的程序烧录及验证。5、 数字逻辑综合设计仿真及验证。实验报告1、基本门电路一、实验目的1、了解基于Verilog的基本门电路的设计及其验证。2、熟悉利用EDA工具进行设计及仿真的流程。3、学习针对实际门电路芯片74HC00、74HC02、74HC04、74HC08、74HC32、74HC86进行VerilogHDL设计的方法。二、实验环境Libero仿真软件。三、实验内容1、掌握Libero软件的使用方法。2、进行针对74系列基本门电路的设计，并完成相应的仿真实验。3、参考教材中相应章节的设计代码、测试平台代码（可自行编程），完成74HC00、74HC02、74HC04、74HC08、74HC32、74HC86相应的设计、综合及仿真。4、提交针对74HC00、74HC02、74HC04、74HC08、74HC32、74HC86（任选一个）的综合结果，以及相应的仿真结果。四、实验结果和数据处理1、所有模块及测试平台代码清单/74HC00代码-与非/ 74HC00.vmodule HC00(A, B, Y); input 3:0 A, B; output3:0 Y; assign Y = (A&B);endmodule/74HC00测试平台代码/ test_00.vtimescale 1ns/1nsmodule test_00; reg 3:0 a,b; wire 3:0 y; HC00 u(a, b, y); initial begin a = 4b0000;b = 4b0001; #10 b = b1;/0010 #10 b = b1;/0100 #10 b = b1;/1000 a = 4b1111;b = 4b0001; #10 b = b1; #10 b = b1; #10 b = b1; endendmodule/74HC02代码-或非/ 74HC02.vmodule HC02(A, B, Y); input 3:0 A, B; output3:0Y; assignY = (A|B);endmodule/74HC02测试平台代码/ test_02.vtimescale 1ns/1nsmodule test_02; reg3:0 a,b,c; wire 3:0 y; HC02 u(a, b, y); initial begin a = 4b1111;c = 4b0001; b = c;c = c1; #10 b = c;c = c1; #10 b = c;c = c1; #10 b = c; a = 4b0000;c = 4b0001; b = c;c = c1; #10 b = c;c = c1; #10 b = c;c = c1; #10 b = c; endendmodule/74HC04代码-非/ 74HC04.vmodule HC04(A, Y); input3:0 A; output3:0Y; assignY = A;endmodule/74HC04测试平台代码/ test_04.vtimescale 1ns/1nsmodule test_04; reg3:0 a; wire 3:0 y; HC04 u (a, y); initial begin a = 4b0001; #10 a = a1; #10 a = a1; #10 a = a1; endendmodule/74HC08代码-与/ 74HC08.vmodule HC08(A, B, Y);input3:0 A, B;output3:0Y;assignY = A&B;endmodule/74HC08测试平台代码/ test_08.vtimescale 1ns/1nsmodule test_08; reg3:0 a,b; wire 3:0 y; HC00 u(a, b, y); initial begin a = 4b0000;b = 4b0001; #10 b = b1; #10 b = b1; #10 b = b1; a = 4b1111;b = 4b0001; #10 b = b1; #10 b = b1; #10 b = b1; endendmodule/74HC32代码-或/74HC32.vmodule HC32(A, B, Y);input 3:0 A, B;output3:0Y;assignY = A|B;endmodule/74HC32测试平台代码/ test_32.vtimescale 1ns/1nsmodule test_32; reg3:0 a,b,c; wire 3:0 y; HC02 u(a, b, y); initial begin a = 4b1111;c = 4b0001; b = c;c = c1; #10 b = c;c = c1; #10 b = c;c = c1; #10 b = c;a = 4b0000;c = 4b0001; b = c;c = c1; #10 b = c;c = c1; #10 b = c;c = c1; #10 b = c; endendmodule/74HC86代码-异或module HC86(A, B, Y);input3:0 A, B;output3:0Y;assignY = AB;endmodule/74HC86测试平台代码/ test_86.vtimescale 1ns/1nsmodule test_86; reg3:0 a, b; wire 3:0 y; HC86 u (a, b, y); initial begin a = 4b0000;b = 4b0001; #10 b = b1; #10 b = b1; #10 b = b1;#10 a = 4b1111;b = 4b0001; #10 b = b1; #10 b = b1; #10 b = b1; endendmodule2、第一次仿真结果（任选一个门，请注明，插入截图，下同）。（将波形窗口背景设为白色，调整窗口至合适大小，使波形能完整显示，对窗口截图。后面实验中的仿真使用相同方法处理）3、综合结果（截图）。（将相关窗口调至合适大小，使RTL图能完整显示，对窗口截图，后面实验中的综合使用相同方法处理）4、第二次仿真结果（综合后）（截图）。回答输出信号是否有延迟，延迟时间约为多少？输出信号有延迟，延迟时间约为0.3ns5、第三次仿真结果（布局布线后）（截图）。回答输出信号是否有延迟，延迟时间约为多少？分析是否有出现竞争冒险。输出信号有延迟，延迟时间约为3ns,没有出现竞争冒险。2、组合逻辑电路一、实验目的1、了解基于Verilog的组合逻辑电路的设计及其验证。2、熟悉利用EDA工具进行设计及仿真的流程。3、学习针对实际组合逻辑电路芯片74HC148、74HC138、74HC153、74HC85、74HC283、74HC4511进行VerilogHDL设计的方法。二、实验环境Libero仿真软件。三、实验内容1、掌握Libero软件的使用方法。2、进行针对74系列基本组合逻辑电路的设计，并完成相应的仿真实验。3、参考教材中相应章节的设计代码、测试平台代码（可自行编程），完成74HC148、74HC138、74HC153、74HC85、74HC283、74HC4511相应的设计、综合及仿真。4、74HC85测试平台的测试数据要求：进行比较的A、B两数，分别为本人学号的末两位，如“89”，则A数为“1000”，B数为“1001”。若两数相等，需考虑级联输入（级联输入的各种取值情况均需包括）；若两数不等，则需增加一对取值情况，验证A、B相等时的比较结果。5、74HC4511设计成扩展型的，即能显示数字09、字母af。6、提交针对74HC148、74HC138、74HC153、74HC85、74HC283、74HC4511（任选一个）的综合结果，以及相应的仿真结果。四、实验结果和数据处理1、所有模块及测试平台代码清单/74HC148代码/ 74HC148.vmodule HC148(EI, In, Out, EO, GS);inputEI;input7:0In;output2:0Out;outputEO, GS;reg2:0Out;regEO, GS;intergerI;always (EI or In)if(EI)beginOut = 3b111; EO = 1;GS = 1;endelseif( In = 8b11111111 )beginOut = 3b111;EO = 0;GS = 1;endelsebeginfor(I = 0;I 8; I = I + 1)beginif( InI)beginOut = I;EO = 1; GS = 0;endendendendmodule/74HC148测试平台代码/ test_148.vtimescale 1ns/1nsmodule test_148;reg ei;reg 7:0turn;wire 7:0in = turn;wire 2:0out;wire eo,gs;HC148 u(ei, in, out, eo, gs);initialbeginei = 1;turn = 8b1;repeat(8)#10 turn = turn1;ei = 0;turn = 8b1;repeat(8)#10 turn = turn1;endendmodule/74HC138代码/ 74HC138.vmodule decoder3_8_1(DataIn,Enable,Eq);input 2:0 DataIn;input Enable;output 7:0 Eq;reg 7:0 Eq;wire2:0 DataIn;integer I;always (DataIn or Enable)beginif(Enable) Eq=0; else for(I=0;I=7;I=I+1) if(DataIn=I) EqI=1; else EqI=0;endendmodule/74HC138测试平台代码/ test_138.vtimescale 1ns/1nsmodule test_138;wire 2:0 out;reg 7:0 in;reg 2:0 ei;HC138 u(out, in, ei);task circle;beginin = 0;repeat(8)#10 in = in + 1;endendtaskinitial beginei = 1;circle(); ei = 0;circle(); ei = 2; repeat(6) begin circle(); #10 ei = ei + 1; endendendmodule/74HC153代码/ 74HC153.vmodule HC153(DateOut, DateIn, Sel, Enable);input3:0DateIn;input1:0Sel;inputEnable;output regDateOut;always (Enable or Sel or DateIn)if(Enable)DateOut = 0;elseDateOut = DateInSel;endmodule/74HC153测试平台代码/ test_153.vtimescale 1ns/1nsmodule test_153();wire out;reg 3:0in;reg 1:0sel;reg ei;HC153 u(out, in, sel, ei);initialbegin ei = 0;sel = 0;in = 4b1010;repeat(4)#10 sel = sel +1; ei = 1;sel = 0;in = 4b1010;repeat(4)#10 sel = sel +1;endendmodule/74HC85代码/ 74HC85.vmodule HC85(DateA, DateB, Cas, Q);input3:0 DateA, DateB;input2:0Cas;output reg2:0Q;intergerI;always (DateA or DateB or Cas)beginif(DateA=DateB)beginif(Cas1)Q = 3b010; else if(Cas=3b000)Q = 3b101; else if(Cas=3b101)Q = 3b000;elseQ = Cas; endelsebeginfor(I=0;IDateBI)Q = 3b100;else if(DateAIDateBI)Q = 3b001;endendendmodule/74HC85测试平台代码/ test_85.vtimescale 1ns/1nsmodule test_85;reg 3:0 a,b;reg 2:0 cas;wire 2:0 res;HC85 u(a, b, cas, res);task cascade_input;begin#0 cas = 0;#10 cas = 1;#10 cas = 3b100;#10 cas = 3b101;#10 cas = 3b010;#10 cas = 3b011;#10 cas = 3b110;#10 cas = 3b111;#10;endendtaskinitialbegina = 4d9;b = a;cascade_input();b = 4d7;cascade_input();endendmodule/74HC283代码/ 74HC283.vmodule HC283(DateA, DateB, Cin, Sum, Cout);input3:0 DateA, DateB;inputCin;output3:0 Sum;outputCout;reg4:0Buf;assign Cout,Sum = Buf;always (DateA or DateB or Cin)Buf = DateA + DateB + Cin + 5d0;endmodule/74HC283测试平台代码/ test_283.vtimescale 1ns/1nsmodule test_283;reg 3:0 a, b;reg in;wire 3:0sum;wire out;interger I;HC283 u(a, b, in, sum, out);task accumulate;begin a = 4b0100;for(I=0;I16;I=I+1)beginb = I;#10;endendtaskinitialbeginin = 0; accumulate();in = 1;accumulate();endendmodule/74HC4511代码/ 74HC4511.vmodule HC4511(DateOut, DateIn, LE, BL_N, LT_N);output7:0DateOut;input3:0DateIn;inputLE, BL_N, LT_N;reg7:0Buf;assignDateOut = Buf;always (DateIn or LE or BL_N or LT_N)beginif(!LT_N)Buf = 8b11111111;else if(!BL_N)Buf = 8b0000000;else if(LE)Buf = Buf;elsecase(DateIn)4d0:Buf = 8b00111111;4d1:Buf = 8b00000110;4d2:Buf = 8b01011011;4d3:Buf = 8b01001111;4d4:Buf = 8b01100110;4d5:Buf = 8b01101101;4d6:Buf = 8b01111101;4d7:Buf = 8b00000111;4d8:Buf = 8b01111111;4d9:Buf = 8b01101111; 4ha:Buf = 8b01110111;4hb:Buf = 8b01111100;4hc:Buf = 8b00111001;4hd:Buf = 8b01011110;4he:Buf = 8b01111001;4hf:Buf = 8b01110001;default:;endcaseend2、第一次仿真结果（任选一个模块，请注明）74HC1483、综合结果4、第二次仿真结果（综合后）。回答输出信号是否有延迟，延迟时间约为多少？输出信号有延迟，延迟时间约为0.5ns5、第三次仿真结果（布局布线后）。回答输出信号是否有延迟，延迟时间约为多少？分析是否有出现竞争冒险。输出信号有延迟，延迟时间约为5.2ns，出现了竞争冒险。3、时序逻辑电路一、实验目的1、了解基于Verilog的时序逻辑电路的设计及其验证。2、熟悉利用EDA工具进行设计及仿真的流程。3、学习针对实际时序逻辑电路芯片74HC74、74HC112、74HC194、74HC161进行VerilogHDL设计的方法。二、实验环境Libero仿真软件。三、实验内容1、熟练掌握Libero软件的使用方法。2、进行针对74系列时序逻辑电路的设计，并完成相应的仿真实验。3、参考教材中相应章节的设计代码、测试平台代码（可自行编程），完成74HC74、74HC112、74HC161、74HC194相应的设计、综合及仿真。4、提交针对74HC74、74HC112、74HC161、74HC194（任选一个）的综合结果，以及相应的仿真结果。四、实验结果和数据处理1、所有模块及测试平台代码清单/74HC74代码/ 74HC74.vmodule HC74(Set_N, Rst_N, Clk, D, Q, Qn);inputSet_N, Rst_N, Clk, D;outputQ, Qn;reg 1:0 Buf;assignQ, Qn = Buf;always (negedge Set_N or negedge Rst_N or posedge Clk)case(Rst_N,Set_N)0: Buf = 2b11;1: Buf = 2b10;2: Buf = 2b01;default:Buf = D,D;endcaseendmodule/74HC74测试平台代码/ test_74.vtimescale 1ns/1nsmodule test_74;reg s, r, clk, d;wire q, qn;HC74 u(s, r, clk, d, q, qn);task clock;repeat(10)begin d = 0; #3;d = 1; #3;endendtaskalwaysbeginclk = 0;#2;clk = 1;#2;endinitialbegin s = 0;r = 1;clock;#5 s = 1;r = 0;clock;#5 s = 0;r = 0;clock;#5 s = 1;r = 1;clock;endendmodule/74HC112代码/ 74HC112.vmodule HC112(Set_N, Rst_N, Clk_N, J, K, Q, Qn);inputSet_N, Rst_N, Clk_N, J, K;outputQ, Qn;regQ;assign Qn = Q;always (negedge Set_N or negedge Rst_N or negedge Clk_N)case(Set_N,Rst_N) 0: Q = 1; 1: Q = 1; 2: Q = 0; default: case(J,K) 0: Q = Q; 1: Q = 0; 2: Q = 1; default: Q = Q;endcaseendcaseendmodule/74HC112测试平台代码/ test_112.vtimescale 1ns/1nsmodule test_112;reg set, res, clk, j, k;wire q, qn;HC112 u(set, res, clk, j, k, q, qn);always#5 clk = clk;task clock;repeat(3)beginj = 0;k = 1;#20; j = 1;k = 0;#20;j = 0;k = 0;#20; j = 1;k = 1;#20;endendtaskinitialbeginclk = 0;set = 0;res = 0;clock;set = 0;res = 1;clock;set = 1;res = 0;clock;set = 1;res = 1;clock;endendmodule/74HC161代码/ 74HC161.vmodule HC161(CP,CEP,CET,MRN,PEN,Dn,Qn,TC); input CP; input CEP,CET; output 3:0Qn; input MRN,PEN; input 3:0Dn; output TC; reg 3:0qaux; always(posedge CP, negedge MRN) begin if(!MRN) qaux=4b0000; else if(!PEN) qaux=Dn; else if(CEP & CET) qaux=qaux+1; else qaux=qaux; end assign TC=(&qaux)&CET; assign Qn=qaux;endmodule/74HC161测试平台代码/ 161testbench.vtimescale 1ns/1nsmodule fre_testbench; reg CP,CEP,CET,MRN; reg LT_N,BI_N,LE; reg 3:0Dn; wire TC; wire 3:0Qn; wire 7:0Seg; initial begin CP=0; CEP=1; CET=1; MRN=0; LT_N=1; BI_N=1; LE=0; #10 MRN=1; end parameter clock_period=20; always #(clock_period/2) CP=CP; initial begin Dn=4b0010; (posedge TC)Dn=4b0100; (posedge TC)Dn=4b1000; (posedge TC)Dn=4b1010; (posedge TC)Dn=4b1110; end frequency fre_test(CP,CEP,CET,MRN,Dn,Seg,LT_N,BI_N,LE,Qn,TC);endmodule /74HC194代码/ 74HC194.vmodule HC194(DataOut, ParIn, SerIn, Sel, Clk, MR_N);output reg3:0 DataOut;input 3:0 ParIn;input1:0 SerIn, Sel;inputClk, MR_N;always (negedge MR_N or posedge Clk)if(MR_N) DataOut = 0;elsecase(Sel) 2b00: DataOut = DataOut; 2b01:If(SerIn1) DataOut = 1b1,DataOut3:1; else DataOut 1; 2b10:if(SerIn0) DataOut = DataOut2:0,1b1; else DataOut = DataOut1; default:DataOut BIA=BIABA=BAB1XXX0XXXXXX1000XXX1XXXXXX00111XX10XXXXX10000XX01XXXXX001101X100XXXX100000X001XXXX00111011100XXX10000100011XXX0011101110100010101000100001001110111011001000000000010100011111111001010注：X为任意状态表4-11 74HC283输入输出状态进位输入4位加数输入4位被加数输入输出加法结果和进位CinA4A3A2A1B4B3B2B1CoutS4S3S2S10000001100011011111111111110001110010010011010001100101010101011101100110000111010011001表4-12 74HC4511输入输出状态使能输入数据输入译码输出LEDCBAabcdefg0XXXXXX111111110XXXXX000000011000001111110110000101100001100010110110111000111111001110010001100111100101101101111001100011111110011111100001101000111111111010011110011110101000000001101011000000011011000000000110110100000001101110000000011011110000000注：X为任意状态表4-13 74HC74输入输出状态输入输出置位输入复位输入CPD1Q01XX1010XX01110011111000XX11注：X为任意状态表4-14 74HC112输入输出状态输入输出置位输入复位输入11J1K1Q01XXX1010XXX0111111011010111101000XXX10注：X为任意状态表4-15 74HC194输入输出状态输入输出模式串行CP并行S1S0DSRDSLD0D1D2D3Q0n+1Q1n+1Q2n+1Q3n+10XXXXXXXXX0000111XXD0D1D2D3Q0nQ1nQ2nQ3n100XXXXXX0Q0nQ1nQ2n1010XXXXX1Q0nQ1nQ2n1011XXXXXQ1nQ2nQ3n0110X0XXXXQ1nQ2nQ3n1110X1XXXXd0 d1d2d3注：X为任意状态表4-16 74HC161输入输出状态输入输出CPCEPCETD3D2D1D0Q3Q2Q1Q0TC0XXXXXXXX000001XX00000000001110D3D2D1D0D3D2D1D0D31111XXXX111111X0X1XXXX000001XX01XXXX00000注：X为任意状态5、数字逻辑综合设计仿真及验证一、实验目的1、进一步熟悉利用EDA工具进行设计及仿真的流程。2、熟悉利用EDA工具中的图形化设计界面进行综合设计。3、熟悉芯片烧录的流程及步骤。4、掌握分析问题、解决问题的综合能力，通过EDA工具设计出能解决实际问题的电路。二、实验环境1、Libero仿真软件。2、DIGILOGIC-2011数字逻辑及系统实验箱。3、Actel Proasic3 A3P030 FPGA核心板及Flash Pro4烧录器。三、实验内容1、编码器扩展实验设计一个电路：当按下小于等于9的按键后，显示数码管显示数字，当按下大于9的按键后，显示数码管不显示数字。若同时按下几个按键，优先级别的顺序是9到0。本实验需要两个编码器74HC148、一个数码显示译码器74HC4511、一个共阴极8段显示数码管LN3461Ax和一个数值比较器74HC85。2、有符号比较器的设计（选做）设计要求：设