Lecture5简单数字电路设计-组合电路.ppt

VerilogHDL语言,华中科技大学计算机科学与技术学院,主讲：胡迪青Email:hudq024QQ:121374333,2,简单数字电路设计,3,设计验证与仿真,VerilogHDL不仅提供描述设计的能力，而且提供对激励、控制、存储响应和设计验证的建模能力。激励和控制可用初始化语句产生。验证运行过程中的响应可以作为“变化时保存”或作为选通的数据存储。最后，设计验证可以通过在初始化语句中写入相应的语句自动与期望的响应值比较完成。要测试一个设计块是否正确，就要用Verilog再写一个测试模块。这个测试模块应包括以下三个方面的内容：测试模块中要调用到设计块，只有这样才能对它进行测试；测试模块中应包含测试的激励信号源；测试模块能够实施对输出信号的检测，并报告检测结果。,4,Simulating/ValidatingHDL,Thesadtruth10%design,90%validationIfyoudoitrightyouwillspend9Xmoretimetesting/validatingadesignthandesigningit.,5,TestbenchExample(contrivedbutvalid),moduletest_and;integerfile,i,code;rega,b,expect,clock;wireout;parametercycle=20;and#4a0(out,a,b);/Circuitundertestinitialbegin:file_blockclock=0;file=$fopen(compare.txt,“r”);for(i=0;i4;i=i+1)begin(posedgeclock)/Readstimulusonrisingclockcode=$fscanf(file,%b%b%bn,a,b,expect);#(cycle-1)/Comparejustbeforeendofcycleif(expect!=out)$strobe(%d%b%b%b%b,$time,a,b,expect,out);end/for$fclose(file);$stop;end/initialalways#(cycle/2)clock=clock;/Clockgeneratorendmodule,6,组合逻辑设计,组合逻辑电路可以有若个输入变量和若干个输出变量，其每个输出变量是其输入的逻辑函数，其每个时刻的输出变量的状态仅与当时的输入变量的状态有关，与本输出的原来状态及输入的原状态无关，也就是输入状态的变化立即反映在输出状态的变化。逻辑电路的各种运算可以用布尔代数来描述狄摩根定律利用狄摩根（DeMorgan）定律可以将积之和形式的电路转换为和之积形式的电路，或反之。,7,组合逻辑的三种通用表示方法结构化（即门级）原理图真值表布尔方程式实例：半加器,8,CombinationalCircuitsComponentInstantiations,CircuitAconnectionofmodules,AlsoknownasstructureAcircuitisasecondwaytodescribea,module,vs.usinganalwaysprocedure,asearlier,InstanceAnoccurrenceofamoduleinacircuitMaybemultipleinstancesofamodule,e.g.,Carsmodules:tires,engine,windows,etc.,with4tireinstances,1engineinstance,6windowinstances,etc.,9,CombinationalCircuitsModuleInstantiations,10,CombinationalCircuitsModuleInstantiations,11,CombinationalCircuitsModuleInstantiations,12,CombinationalCircuitStructureSimulatinggtheCircuit,SametestbenchformatforBeltWarnmoduleasforearlierAnd2module,13,CombinationalCircuitStructureSimulatinggtheCircuit,14,CombinationalCircuitStructureSimulatinggtheCircuit,timescale1ns/1nsmoduleTestbench();regK_s,P_s,S_s;wireW_s;BeltWarnCompToTest(K_s,P_s,S_s,W_s);initialbegin,MoreontestbenchesNotethatasinglemoduleinstantiationstatementusedregandwiredeclarations(K_s,P_s,S_s,W_s)usedbecauseprocedurecannotaccessinstantiatedmodules,=0;S_sP_s=1;P_s=1;P_s=1;,=0;S_s=0;S_s=0;S_s=1;,K_s=0;P_s#10K_s=0;#10K_s=1;#10K_s=1;endendmodule,portsdirectlyInputsdeclaredasregssocanassignvalues(whichareheldbetweenassignments)Notemoduleinstantiationstatement,andprocedurecanbothappearinonemodule,15,CombinationalBehaviortoStructure,16,CombinationalBehaviortoStructureAlwaysProcedureswithAssignmentStatements,17,CombinationalBehaviortoStructureProcedureswithAssignmentStatements,ProceduralassignmentstatementAssignsvaluetovariableRightsidemaybeexpressionofoperators,timescale1ns/1nsmoduleBeltWarn(K,P,S,W);inputK,P,S;outputW;regW;,Built-inbitoperatorsinclude,end,18,CombinationalBehaviortoStructureProcedureswithAssignmentStatements,Proceduremayhavemultipleassignmentstatements,timescale1ns/1nsmoduleTwoOutputEx(A,B,C,F,G);,inputA,B,C;outputFF,G;regF,G;always(A,B,C)beginF=(Bendendmodule,19,CombinationalBehaviortoStructureProcedureswithIf-ElseStatements,Processmayuseif-elsestatements(a.k.a.conditionalstatements),if(expression)Ifexpressionistrue(evaluatestononzerovalue),executecorrespondingstatement(s)Iffalse(evaluatesto0),executeelsessstatement(elsepartisoptional)Exampleshowsuseofoperator=,timescale1ns/1nsmoduleBeltWarn(K,P,S,W);inputK,P,S;outputW;regW;always(K,P,S)beginif(Kelse,W=0;,logicalequality,returnstrue/false(actually,returns1or0),endendmodule,Trueisnonzerovalue,falseiszero,20,CombinationalBehaviortoStructureProcedureswithIf-ElseStatements,Morethantwopossibilities,Handledbystringingif-elsestatementstogetherKnownasif-else-ifconstruct,Example:4x1muxbehavior,timescale1ns/1nsmoduleMux4(I3,I2,I1,I0,S1,S0,D);inputI3,I2,I1,I0;,inputS1,S0;outputD;,SupposeS1S0changeto01,SupposeS1S0changeto01ifsexpressionisfalseelsesstatementexecutes,whichisanifstatementwhoseexpressionistrue,regD;always(I3,I2,I1,I0,S1,S0)beginif(S1=0,elseif(S1=1,Note:Thefollowingindentationshowsifstatementnesting,butisunconventional:if(S1=0else,if(S1=0else,values,returnstrue/false),21,CombinationalBehaviortoStructureProcedureswithIf-ElseStatements,22,CombinationalBehaviortoStructure,23,CombinationalBehaviortoStructureCommonPitfallMissingInputsfromEventControlExpression,24,CombinationalBehaviortoStructureCommonPitfallMissingInputsfromEventControlExpression,Verilogprovidesmechanismtohelpavoidthispitfall,*impliciteventcontrolexpressionAutomaticallyaddsallnetsandvariablesthatarereadbythecontrolledstatementorstatementgroupThus,*inexampleisequivalentto(S1,S0,I0,I1,I2,I3),timescale1ns/1nsmoduleMux4(I3,I2,I1,I0,S1,S0,D);inputI3,I2,I1,I0;inputS1,S0;outputD;regD;,(*)alsoequivalentalways*beginif(S1=0endendmodule,25,CombinationalBehaviortoStructureCommonPitfallOutputnotAssignedonEveryPass,26,CombinationalBehaviortoStructureCommonPitfallOutputnotAssignedonEveryPass,Samepitfalloftenoccursduetonotconsideringallpossibleinputcombinationsif(I1=0endelseif(I1=1D2=1;,D1=0;D0=0;,Lastelsemissing,sonotall,end,inputcombinationsarecovered(i.e.,I1I0=11notcovered),