ADDA等一些芯片的verilog程序

/*AD0809modulev1.0workupto5Msample=25us40khzfornormalclk=2.5Msample=30us33khz*/modulead0809(clkin,adclk,eoc,st,ale,datain,oe,dataout);inputclkin;inputeoc;input7:0datain;outputst;outputale;outputoe;outputadclk;output7:0dataout;regadclk;reg7:0dataout;regst;regoe;regale;/frequencedividerforADparameterDiv_adclk=8d9;/(9+1)*2=20adclk=2.5MparameterDiv_clk_state=4d4;/(4+1)*2=10clk_state=5Mreg8:0div_cnt_ad;/frequencedivcntreg3:0div_cnt_state;regclk_state;always(negedgeclkin)beginif(div_cnt_ad!=Div_adclk)div_cnt_ad=div_cnt_ad+1b1;elsebegindiv_cnt_ad=0;adclk=adclk;endif(div_cnt_state!=Div_clk_state)div_cnt_state=div_cnt_state+1b1;elsebegindiv_cnt_state=0;clk_state=clk_state;endend/*ADconvert*/reg3:0state;reg7:0delay;initialbeginstate=4d0;endalways(negedgeclk_state)begincase(state)4d0:begin/clearallst=1b0;oe=1b0;ale=1b0;delay=8h00;state=4d1;end4d1:begin/alelatchale=1b1;state=4d2;end4d2:begin/strasingst=1b1;state=4d3;end4d3:begin/alefallingale=1b0;state=4d4;end4d4:begin/stfallingst=1b0;state=4d5;end4d5:begin/eocdelayafterst;8clock+2us=26stata_clkdelay=delay+1b1;if(delay=8d26)state=4d6;elsestate=4d5;end4d6:begin/testeoc(convetefinished);if(eoc)state=4d7;elsestate=4d6;end4d7:begin/outenableoe=1b1;state=4d8;4d8:begin/takedatadataout=datain;state=4d9;end4d9:begin/outunable;returnoe=1b0;state=4d0;enddefault:state=4d0;endcaseendendmodule/*clk=5MhzT=0.2usthedistance=0.2*1000_000*data*340m/s*/modulechao(clk,start,reset,trig,echo,data,success,time_out);inputclk,start,reset,echo;outputtrig,data,success,time_out;regtrig,time_out,success;reg31:0data;=4d1;reg3:0state;parameterPrepareparameterDelay_trig=4d2;parameterEcho_raising=4d3;parameterEcho_falling=4d4;parameterTime_out=4d5;parameterSuccess=4d6;reg7:0dely;/60*0.2=12usreg31:0timer;/iftimerisbiggerthan0x1e848(farthan4.0m),timeoutalways(negedgeclkornegedgereset)beginif(!reset)beginstate=Prepare;endelsebegincase(state)Prepare:begintimer=32h0000_0000;trig=1b0;/success=1b0;/time_out=1b0;if(!start)begintrig=1b1;/trigthedevicedely=8b0000_0000;state=Delay_trig;endelsebeginstate=Prepare;endendDelay_trig:begin/delay12usdely=dely+1b1;if(dely!=8d60)begin/60state=Delay_trig;endelsebegintrig=1b0;/endoftrigstate=Echo_raising;endendEcho_raising:begin/waitforechorassingtimer=timer+1b1;if(echo)begintimer=32d0;state=Echo_falling;endelsebeginstate=32d2250)begin/450ustimer=32d0;state=Prepare;endelsebeginif(echo)begintimer=32d0;state=Echo_falling;endelsebeginstate=Echo_raising;endend*/endEcho_falling:begin/waitforechofallingortimeouttimer=32d120000)begin/outof10mstate=Time_out;endelsebeginif(!echo)begindata=timer;state=Success;endelsebeginstate=Echo_falling;endendendTime_out:begintime_out=time_out;state=Prepare;endSuccess:beginsuccess=success;state=Prepare;enddefault:beginstate=Prepare;endendcaseend/endofifendendmodule/*clk=5MhzT=0.2usthedistance=0.2*1000_000*data*340m/s*/modulechao(clk,start,reset,trig,echo,data,success,time_out);inputclk,start,reset,echo;outputtrig,data,success,time_out;regtrig,time_out,success;reg31:0data;reg3:0state;parameterDelay_trig=4d2;parameterEcho_raising=4d3;parameterEcho_falling=4d4;parameterTime_out=4d5;parameterSuccess=4d6;reg7:0dely;/60*0.2=12usreg31:0timer;/iftimerisbiggerthan0x1e848(farthan4.0m),timeoutalways(negedgeclkornegedgereset)beginif(!reset)beginstate=Prepare;endelsebegincase(state)Prepare:begintimer=32h0000_0000;trig=1b0;/success=1b0;/time_out=1b0;if(!start)begintrig=1b1;/trigthedevicedely=8b0000_0000;state=Delay_trig;endelsebeginstate=Prepare;endendDelay_trig:begin/delay12usdely=dely+1b1;if(dely!=8d60)begin/60state=Delay_trig;endelsebegintrig=1b0;/endoftrigstate=Echo_raising;endendEcho_raising:begin/waitforechorassingtimer=timer+1b1;if(echo)begintimer=32d0;state=Echo_falling;endelsebeginstate=32d2250)begin/450ustimer=32d0;state=Prepare;endelsebeginif(echo)begintimer=32d0;state=Echo_falling;endelsebeginstate=Echo_raising;endend*/endEcho_falling:begin/waitforechofallingortimeouttimer=32d120000)begin/outof10mstate=Time_out;endelsebeginif(!echo)begindata=timer;state=Success;endelsebeginstate=Echo_falling;endendTime_out:begintime_out=time_out;state=Prepare;endSuccess:beginsuccess=success;state=Prepare;enddefault:beginstate=Prepare;endendcaseend/endofifendendmodule/*max358modlulev1.0sclk=25Mconvert=0.588M2010/8/10*/modulemax538(clk,databus,din,sclk,cs);/*direction*/inputclk;outputdin;outputsclk;outputcs;input15:0databus;/*attribute*/regdin;regsclk;regcs;/*inner*/reg15:0datatemp;reg7:0state;reg3:0cnt16;reg3:0delay;/*statedefine*/parameterPrepare=8d1;parameterCs_0=8d2;parameterCs_1=8d4;parameterSclk_1=8d8;parameterSclk_0=8d16;parameterDelay=8d32;always(negedgeclk)begincase(state)Prepare:begin/clearcs=1b1;sclk=1b0;cnt16=4b0000;delay=4b0000;datatemp=databus;state=Cs_0;Cs_0:begincs=1b0;/selectthechipdin=datatemp15;/offerdatafirststate=Sclk_1;endSclk_1:beginsclk=1b1;/raisingtakethedatadatatemp=datatemp1;/shiftleftstate=Sclk_0;endSclk_0:beginsclk=1b0;/fallingdin=datatemp15;/offerdatacnt16=cnt16+4b0001;if(cnt163&cnt162&cnt161&cnt160)begin/16state=Delay;endelsestate=Sclk_1;endDelay:begindelay=delay+4b0001;cs=1;if(delay3)state=Prepare;elsestate=Delay;enddefault:state=Prepare;endcaseenda/*tlc1549v1.4adclk=0.333Msample=20K2011/8/9*/moduletlc1549(reset,clk50M,adclk,adcs,addata,databus);/*directiondefine*/inputreset;inputclk50M;inputaddata;outputadclk;outputadcs;outputdatabus;/*attribute*/regadclk;regadcs;reg15:0databus;/输出数据/innerregisterreg15:0datatmp;/暂存数据reg3:0cnt;/计数器统计十位reg9:0state;/状态热码reg3:0delay;/conveterdelaycounterparameterAdcs_1=10d1;parameterAdcs_0=10d2;parameterClear=10d4;parameterConvert_1=10d8;parameterConvert_0=10d16;parameterFinish=10d32;parameterReset=10d64;parameterDelay=10d128;parameterWaitdata=10d256;parameterDiv=8d24;/div=(24+1)*2=50fre=50M/50=1M;adclk=0.333Mreg7:0div_cnt;/frequencedivcntregclkbuf;wireclkin;/frequencedividealways(negedgeclk50M)beginif(div_cnt!=Div)div_cnt=div_cnt+1;elsediv_cnt=0;endalways(negedgeclk50M)beginif(div_cnt=0)clkbuf=clkbuf;endassignclkin=clkbuf;/adconvertalways(negedgeclkin)begincase(state)Adcs_1:/stopI/Oclockbeginadcs=1;state=Adcs_0;endAdcs_0:/enablecontrlbeginadcs=0;state=Clear;begindatatmp=16h0000;cnt=0;delay=0;adclk=1b1;state=Convert_0;endConvert_0:beginadclk=1b0;/fallingedgedatatmp=datatmp1;state=Waitdata;endWaitdata:beginif(addata)datatmp0=1;/thisisinportantstate=Convert_1;endConvert_1:beginif(!reset)state=Reset;elsebegincnt=cnt+1b1;if(cnt3&cnt0)begindatabus=datatmp&16h3fff;/takethedataadclk=1b1;/rasingedgestate=Finish;endelsebeginadclk=1b1;/rasingedgestate=Convert_0;endendendFinish:beginadcs=1;state=Delay;endDelay:begindelay=delay+1;if(delay3&delay2)/1100state=Reset;elsestate=Delay;endReset:beginstate=Adcs_1;enddefault:state=Reset;endcaseendendmodule/clk为16倍波特频率。E会置1。/外部可在E的下降沿读走接收到数据的sbuff，在下次数据来时，moduleuartrec(clk,e,rx,sbuff);inputclk,rx;output7:0sbuff;outpute;rege;reg7:0sbuff;assignrx2=rx;initialbeginstate=0;e=1;endparameterStartparameterS_fparameterS_b=8b0000_0001;=8b0000_0010;=8b0000_0100;/innersingnalreg9:0sbuff_tmp;/10bitmodereg8:0state;reg8:0delay;reg3:0bits;always(negedgeclk)begincase(state)Start:begine=1b1;if(!rx)begin/waitforstartbitdelay=8d0;bits=4d0;sbuff_tmp=10d0;state=S_f;endelsestate=Start;endS_f:begindelay=delay+8d1;if(delay=8d7)beginsbuff_tmp1;if(rx)sbuff_tmp9=1b1;elsesbuff_tmp9=1b0;state=S_f;elseif(delay=8d15)begindelay=8d0;bits=bits+4d1;if(bits=4d9)beginbits=4d0;e=1b0;state=S_b;endendelsestate=S_f;endS_b:begine=1b0;sbuff=sbuff_tmp8:1;state=Start;/stopenddefault:state=Start;endcaseendendmodule/clk为16倍波特频率。/E下降锁存数据sbuff开始发送,busy=0,忙/发送完后，busy置1。moduleuartsend(clk,e,sbuff,tx,busy);inputclk;reg7:0count;input7:0sbuff;reg7:0buff;inpute;outputbusy;regbusy;outputtx;regtx;reg2:0state;initialbeginstate=0;tx=1;busy=1;endalways(negedgeclk)begincount=count+1;case(state)0:beginif(e=0)beginstate=1;count=0;buff=sbuff;tx=0;/start0;busy=0;endend1:beginif(count3:0=15)beginif(count7:4=4b1000)beginstate=3;tx=1;/end1endelsebeginstate=2;if(buff&8b1)tx=1;elsetx=0;endendend2:beginbuff1;state=1;end3:beginif(count3:0=15)beginbusy=1;if(e)state=0;elsestate=3;enddefault:state=0;endcaseendendmodule