A5191HRT型HART调制解调器毕业论文外文翻译

西安工程大学本科毕业设计（译文） 译 文 原文题目： A5191HRT AMIS HART Modem 译文题目： A5191HRT型HART调制解调器 学 院： 电子信息学院 专业班级： 自动化2009级04班 学生姓名： 学 号： 40905010435 22西安工程大学本科毕业设计（译文）A5191HRT AMIS HART Modem1. FeaturesCan be used in designs presently using the SYM20C15Single-chip, half-duplex 1200 bits per second FSK modemBell 202 shift frequencies of 1200Hz and 2200Hz3.3V - 5.0V power supplyTransmit-signal wave shapingReceive band-pass filterLow power: optimal for intrinsically safe applicationsCMOS compatibleInternal oscillator requires 460.8kHz crystal or ceramic resonatorMeets HART physical layer requirementsIndustrial temperature range of -40C to +85CAvailable in 28-pin PLCC and 32-pin LQFP packages2. DescriptionThe A5191HRT is a single-chip, CMOS modem for use in highway addressable remote transducer (HART) field instruments and masters. The modem and a few external passive components provide all of the functions needed to satisfy HART physical layer requirements including modulation, demodulation, receive filtering, carrier detect, and transmit-signal shaping. The A5191HRT is pin-compatible with the SYM20C15. See the Pin Description and Functional Description sections for details on pin compatibility with the SYM20C15.The A5191HRT uses phase continuous frequency shift keying (FSK) at 1200 bits per second. To conserve power the receive circuits are disabled during transmit operations and vice versa. This provides the half-duplex operation used in HART communications.Figure 2-1 28-Pin PLCC Pinout Diagrams (green & non-green)Figure 2-2 32-Pin LQFP Pinout Diagrams (green & non-green)Table 2-1 Pinout Summary 28-Pin PLCC, A5191HRTP/Pg (12197-504/508)Pin N0.Signal NameTypePin description1TEST1InputConnect to VSS2TEST2-No connect3TEST3-No connect4TEST4-No connect5TEST5InputConnect to VSS6INRESETInputReset all digital logic when low7TEST7InputConnect to VSS8TEST8InputConnect to VSS9TEST9InputConnect to VSS10OTXAOutputOutput transmit analog, FSK modulated HART transmit signal to 4-20mA loop interface circuit11IAREFInputAnalog reference voltage12ICDREFInputCarrier detect reference voltage13OCBIASOutputComparator bias current14TEST10InputConnect to VSS15VDDAPowerAnalog supply voltage16IRXAInputFSK modulated HART receive signal from 4-20mA loop interface circuit17ORXAFOutputAnalog receive filter output18IRXACInputAnalog receive comparator input19OXTLOutputCrystal oscillator output20IXTLInputCrystal oscillator input21VSSGroundGround22VDDPowerDigital supply voltage23INRTSInputRequest to sent24ITXDInputInput transmit date, transmitted HART data stream from UART25TEST11-No connect26ORXDOutputReceived demodulated HART data to UART27OCDOutputCarrier detect output28TEST12-No connectTable 2-2 Pinout Summary 32-Pin LQFP, A5191HRTL/Lg (12197-503/507)Pin No.Signal NameTypePin Description1TEST5InputConnect to VSS2INRESETInputReset all digital logic when low, connect to VDD for normal operation3TEST7InputConnect to VSS4TEST8InputConnect to VSS5TEST9InputConnect to VSS6VSSGroundDigital ground7OTXAOutputOutput transmit analog, FSK modulated HART transmit signal to 4-20mA loop interface circuit8IAREFInputAnalog reference voltage9ICDREFInputCarrier detect reference voltage10OCBIASOutputComparator bias current11TEST10InputConnect to VSS12VSSAGroundAnalog ground13VDDAPowerAnalog supply voltage14IRXAInputFSK modulated HART receive signal from 4-20mA loop interface circuit15ORXAFOutputAnalog receive filter output16IRXACInputAnalog receive comparator input17OXTLOutputCrystal oscillator output18IXTLInputCrystal oscillator input19VSSAGroundAnalog ground20VSSGroundDigital ground21VDDPowerDigital supply voltage22INRTSInputRequest to send23ITXDInputInput transmit data, transmitted HART data stream from UART24TEST11-No connect25ORXDOutputReceived demodulated HART data to UART26OCDOutputCarrier detect output27TEST12-No connect28TEST1InputConnect to VSS29TEST2-No connect30VDDPowerDigital supply voltage31TEST3-No connect32TEST4-No connect3. Pin DescriptionsTable 3-1 Pin DescriptionsSymbolPin NameDescriptionIAREFAnalog Reference VoltageAnalog input sets the dc operating point of the operational amplifiers and comparators and is usually selected to split the dc potential between VDD and VSS. ICDREFCarrier Detect Reference VoltageAnalog input controls at which level the carrier detect (OCD) becomes active. This is determined by the dc voltage difference between ICDREF and IAREF. Selecting ICDREF - IAREF equal to 0.08 VDC will set the carrier detect to a nominal 100 mVp-pINRESETReset Digital LogicWhen at logic low (VSS) this input holds all the digital logic in reset. During normal operation INRESET should be at VDD. INRESET should be held low for a minimum of 10nS after VDD = 2.5V as shown in Figure 3INRTSRequest to SendActive-low input selects the operation of the modulator. OTXA is enabled when this signal is low. This signal must be held high during power-upIRXAAnalog Receive InputInput accepts the 1200/2200Hz signals from the external filterIRXACAnalog Receive Comparator InputPositive input of the carrier detect comparator and the receiver filter comparatorITXDDigital Transmit Input (CMOS)Input to the modulator accepts digital data in NRZ form. When ITXD is low, the modulator output frequency is 2200Hz. When ITXD is high, the modulator output frequency is 1200Hz.IXTLOscillator InputInput to the internal oscillator must be connected to a parallel mode 460.8kHz ceramic resonator when using the internal oscillator or grounded when using an external 460.8kHz clock signalOCBIASComparator Bias CurrentThe current through this output controls the operating parameters of the internal operational amplifiers and comparators. For normal operation, OCBIAS current is set to 2.54A.OCDCarrier Detect OutputOutput goes high when a valid input is recognized on IRXA. If the received signal is greater than the threshold specified on ICDREF for four cycles of the IRXA signal, the valid input is recognized.ORXAFAnalog Receive Filter OutputSignal is the square wave output of the receiver high-pass filterORXDDigital Receive Output (CMOS)Signal outputs the digital receive data. When the received signal (IRXA) is 1200Hz, ORXD outputs logic high. When the received signal (IRXA) is 2200Hz, ORXD outputs logic low. ORXD is qualified internally with OCD.OTXAAnalog Transmit OutputOutput provides the trapezoidal signal controlled by ITXD. When ITXD is low, the output frequency is 2200Hz. When ITXD is high, the output frequency is 1200Hz. This output is active when INRTS is low and 0.5 VDC when INRTS is high.OXTLOscillator OutputOutput from the internal oscillator must be connected to an external 460.8kHz clock signal or to a parallel mode 460.8kHz ceramic resonator when using the internal oscillatorTEST(12:1)Factory TestFactory test pins; for normal operation, tie these signals as per Table 1 and Table 2VDDDigital PowerPower for the digital modem circuitryVDDAAnalog Supply VoltagePower for the analog modem circuitryVSSGroundAnalog and digital groundVSSAAnalog GroundFigure 3-1 Reset TimingNote:This signal is also present on the LSI 20C15. It is labeled as Test6. The 20C15 data sheet mentions the reset function of this pin but does not emphasize its use to reset the chip. Reliable operation of the modem requires a hardware reset as shown in Figure 3. This is true for the AMIS 12197-503 and 12197-504 as well as the LSI 20C15.4. Functional DescriptionThe A5191HRT is a functional equivalent of the SYM20C15 HART Modem. It contains a transmit data modulator and signal shaper, carrier detect circuitry, analog receiver and demodulator circuitry and an oscillator, as shown in Figure 4-1. The internal HART modem modulates the transmit-signal and demodulates the receive signal. The transmit-signal shaper enables the A5191HRT to transmit a HART compliant signal. The carrier is detected by comparing the receiver filter output with the difference between two external voltage references. The analog receive circuitry band-pass filters the received signal for input to the modem and the carrier detect circuitry. The oscillator provides the modem with a stable time base using either a simple external resonator or an external clock source. Figure 4-1 A5191HRT Block Diagram4.1 A5191HRT LogicThe modem consists of a modulator and demodulator. The modem uses shift frequencies of nominally 1200Hz (for a 1) and 220Hz (for a 0). The bit rate is 1200 bits/second.4.1.1 ModulatorThe modulator accepts digital data in NRZ form at the ITXD input and generates the FSK modulated signal at the OTXA output. INRTS must be a logic low for the modulator to be active.4.1.2 DemodulatorThe demodulator accepts an FSK signal at the IRXA input and reproduces the original modulating signal at the ORXD output. The nominal bit rate is 1200 bits per second. Figure 4-2 illustrates the demodulation process.Figure 4-2 Demodulator Signal Timing The output of the demodulator is qualified with the carrier detect signal (OCD), therefore, only IRXA signals large enough to be detected (100mVp-p typically) by the carrier detect circuit produce received serial data at ORXD.Maximum demodulator jitter is 12 percent of one bit given input frequencies within HART specifications, a clock frequency of 460.8kHz (1.0 percent) and zero input (IRXA) asymmetry.4.2 Transmit-Signal ShaperThe transmit-signal shaper generates a HART compliant FSK modulated signal at OTXA. Figure 4-3 and Figure 4-4 show the transmit-signal forms of the A5191HRT.For IAREF = 1.235 VDC, OTXA will have a voltage swing from approximately 0.25 to 0.75 VDC.Figure 4-3 OTXA Waveform (1200Hz) Figure 4-4 OTXA Waveform (2200Hz)4.3 Carrier Detect CircuitryThe carrier detect comparator shown in Figure 4-5 generates logic low output if the IRXAC voltage is below ICDREF. The comparator output is fed into a carrier detect block (see Figure 4). The carrier detect block drives the carrier detect output pin OCD high if INRTS is high and four consecutive pulses out of the comparator have arrived. OCD stays high as long as INRTS is high and the next comparator pulse is received in less than 2.5ms. Once OCD goes inactive, it takes four consecutive pulses out of the comparator to assert OCD again. Four consecutive pulses amount to 3.33ms when the received signal is 1200Hz and to 1.82ms when the received signal is 2200HZ.4.4 Analog Receiver Circuitry4.4.1 Voltage ReferencesThe A5191HRT requires two voltage references, IAREF and ICDREF. IAREF sets the dc operating point of the internal operational amplifiers and comparators. A 1.235 VDC reference (Analog Devices AD589) is suitable as IAREF.The level at which OCD (carrier detect) becomes active is determined by the dc voltage difference (ICDREF - IAREF). Selecting a voltage difference of 0.08 VDC will set the carrier detect to a nominal 100 mVp-p.4.4.2 Bias Current ResistorThe A5191HRT requires a bias current resistor to be connected between OCBIAS and VSS. The bias current controls the operating parameters of the internal operational amplifiers and comparators.The value of the bias current resistor is determined by the reference voltage IAREF and the following formula:The recommended bias current resistor is 500K when IAREF is equal to 1.235 VDC.In Figure 4-5 all external capacitor values have a tolerance of 5 percent and the resistors have a tolerance of 1 percent, except the 3M which has a tolerance of 5 percent. External to the A5191HRT, the filter exhibits a three-pole, high-pass filter at 624Hz and a one-pole, low-pass filter at 2500Hz. Internally, the A5191HRT has a high-pass pole at 35Hz and a low-pass pole at 90kHz. The low-pass pole can vary as much as 30 percent. The input impedance of the entire filter is greater than 150M at frequencies below 50kHz.Figure 4-5 Receive Filter Schematic 4.5 OscillatorThe A5191HRT requires a 460.8kHz clock signal on OXTL. This can be provided by an external clock or external components may be connected to the A5191HRT internal oscillator.4.5.1 Internal Oscillator OptionThe oscillator cell will function with either a 460.8kHz crystal or ceramic resonator. A parallel resonant ceramic resonator can be connected between OXTL and IXTL. Figure 4-6 illustrates the crystal option for clock generation using a 460.8kHz (I percent tolerance) parallel resonant crystal and two tuning capacitors. The actual values of the capacitors may depend on the recommendations of the manufacturer of the resonator. Typically, capacitors in the range of 100pF to 470pF are used.4.5.2 External Clock OptionIt may be desirable to use an external 460.8kHz clock as shown in Figure 4-7rather than the internal oscillator because of the high cost and low availability of ceramic resonators. In addition, the A5191HRT consumes less current when an external clock is used. Minimum current consumption occurs with the clock connected to OXTL and IXTL connected to VSS.Figure 4-6 Crystal OscillatorFigure 4-7 Oscillator with External ClockA5191HRT型HART调制解调器1. 主要特点可用于设计目前正在使用的SYM20C15单芯片，半双工1200 bits调制解调器每秒FSK贝尔202的1200Hz和2200Hz移频3.3V - 5.0V电源发送信号波形整形接收频带通滤波器低功耗：为本质安全应用的最佳选择CMOS兼容内部振荡器需要460.8kHz 晶体或陶瓷谐振器符合HART协议物理层要求工业温度范围为-40C +85C可在28-pin PLCC和32-pin LQFP包2. 描述A5191HRT是一款具有CMOS调制解调器的单片机，可用于HART协议领域中的仪器和高端仪器。调制解调器和几个外部无源元件提供了所有用于满足HART协议物理层需要的功能，包括调制、解调、接收滤波器、载波检测电路、发送信号整形电路。A5191HRT型是sym20c15的引脚兼容。sym20c15引脚兼容详情见引脚描述和功能描述。A5191HRT使用连续周期的移频键控，频率为1200b/s。为了节省电能，接收电路期间禁用发送操作，反之亦然。这提供了用于HART通信的半双工操作。图2-1 28-Pin PLCC引脚输出图（绿色和非绿色）图 2-2 32-Pin LQFP引脚输出图（绿色和非绿色）表2-1 28引脚引脚输出功能，A5191HRTP/Pg (12197-504/508)引脚号信号名称类型引脚说明1TEST1输入连接到VSS2TEST2-无连接3TEST3-无连接4TEST4-无连接5TEST5输入连接到VSS6INRESET输入复位时，所有的数字逻辑低7TEST7输入连接到VSS8TEST8输入连接到VSS9TEST9输入连接到VSS10OTXA输出输出传输模拟，FSK调制的HART信号传输到接口电路回路4-20mA11IAREF输入模拟参考电压12ICDREF输入载波参考电压检测13OCBIAS输出当前比较偏置14TEST10输入连接到VSS15VDDA电源模拟电源电压16IRXA输入FSK的HART调制接收信号接口电路回路4-20mA17ORXAF输出模拟接收滤波器输出18IRXAC输入模拟接收比较器输入19OXTL输出晶体振荡器输出20IXTL输入晶体振荡器输入21VSS接地接地22VDD电源数字供电电压23INRTS输入请求发送24ITXD输入输入发送日期，发送HART数据流从UART25TEST11-无连接26ORXD输出HART数据接收解调到UART27OCD输出载波检测输出28TEST12-无连接表 2-2 32引脚引脚输出功能，A5191HRTl/Lg (12197-503/507)引脚号信号名称类型引脚说明1TEST5输入连接到VSS2INRESET输入复位所有逻辑低电平时，连接到VDD正常运作3TEST7输入连接到VSS4TEST8输入连接到VSS5TEST9输入连接到VSS6VSS接地数字地7OTXA输出输出传输模拟，FSK调制的HART信号传输到接口电路回路4-20mA8IAREF输入模拟参考电压9ICDREF输入载波参考电压检测10OCBIAS输出当前比较偏置11TEST10输入连接到VSS12VSSA接地模拟地13VDDA电源模拟电源电压14IRXA输入FSK的HART调制接收信号接口电路回路4-20mA15ORXAF输出模拟接收滤波器输入16IRXAC输入模拟接收比较器输入17OXTL输出晶体振荡器输出18IXTL输入晶体振荡器输入19VSSA接地模拟地20VSS接地数字地21VDD电源数字供电电压22INRTS输入请求发送23ITXD输入输入传输数据，传输数据流从UART的HART24TEST11-无连接25ORXD输出HART数据接收解调到UART26OCD输出载波检测输出27TEST12-无连接28TEST1输入连接到VSS29TEST2-无连接30VDD电源数字供电电压31TEST3-无连接32TEST4-无连接3. 0 引脚说明表3-1 引脚说明符号引脚名称说明IAREF模拟参考电压模拟输入设置直流操作点的运算放大器和比较器,通常选择分裂直流电压VSS和VDD之间。ICDREF载波参考电压检测模拟输入控件在哪个层次的载波检测(OCD)变得活跃。这是由直流电压ICDREF和IAREF之间的区别。选择ICDREF - IAREF等于0.08 VDC将载波检测到一个名义为100mVp-p。INRESET数字逻辑复位当输入为低电平（VSS）时所有数字逻辑信号复位。在正常操作INRESET应该在VDD。INRESET应该持有低至10 ns VDD = 2.5 v后如图3。INRTS请求发送校验输入选择操作的调制器。启用OTXA当这个信号是低的，此信号必须持有上电时高。IRXA模拟接收输入接受从外部滤波器输入1200/2200Hz信号。IRXAC模拟接收比较器输入正输入的载波检测比较器和接收滤波器比较器。ITXD数字传输输入(CMOS)调制器的输入形式接纳NRZ数字数据。当ITXD低，调制器输出频率为2200Hz。当ITXD高，调制器的输出频率1200Hz。IXTL振荡器输入内部振荡器的输入必须连接到并行模式460.8kHz陶瓷谐振器，当使用内部振荡器或接地时使用外部460.8kHz时钟信号。OCBIAS当前比较偏置通过这个输出电流控制内部的运行参数运算放大器和比较器。正常工作时，OCBIAS电流设置为2.54A。OCD载波检测输出输出有效高电平时一个有效的输入是在IRXA确认。如果接收到的信号大于阈值指定在ICDREF四个周期的IRXA信号,有效的输入是公认的。ORXAF模拟接收滤波器输出接收机高通滤波器信号是方波输出。ORXD数字接收输出(CMOS)输出数字信号接收数据。当接收到的信号(IRXA)是1200Hz，ORXD输出逻辑为高电平。当接收到的信号(IRXA)是2200Hz, ORXD输出逻辑为低电平。 ORXD是合格的内部OCD。OTXA模拟发射输出输出提供了梯形信号控制的ITXD。当ITXD低,输出频率为2200赫兹。当ITXD高、输出频率为1200赫兹。当INRTS高时，输出是激活在INRTS低和0.5 VDC。OXTL振荡器输出从内部振荡器的输出必须连接到一个外部时钟460.8kHz信号或并行模式460.8kHz陶瓷谐振器在使用内部振荡器时。TEST(12:1)出厂检验工厂正常操作测试。查询这些信号按表1和表2。 VDD数字电源数字调制解调器的电源电路VDDA模拟电源电压模拟调制解调器的电源电路VSS接地模拟和数字地VSSA模拟地图 3-1 复位时序图注意：这个信号也对LSI 20C15使用。目前它被标记为Test6。20C15数据表中提到这个引脚复位功能，但不强调其使用复位芯片。调制解调器的可靠的操作需要一个硬件复位如图3。比如AMIS 12197-503、12197-504以及LSI 20C15。4. 功能描述A5191HRT与HART协议SYM20C15调制解调器功能相等。它包括了一个数据传输调制器，信号整形，载波检测电路，模拟接收器和解调器电路和振荡器，如图4-1所示。内部HART调制解调器调制发射信号和解调接收信号。发射信号整形器能够使A5191HRT发送符合HART的信号。载波信号则是通过对比两个外部参考电压接受滤波器的输出差异被检测出来。模拟接收电路中的带通滤波器将过滤后的接收信号输入到调制协调器和载波检测电路。振荡器为调制协调器提供了一个可以使用简单的外部谐振器或者外部时钟来源的稳定的时基。图 4-1 A5191HRT框图4.1 A5191HRT 体系调制解调器包括一个调制器和解调器。调制解调器名义上使用的的转换频率1200Hz（1）和220Hz（0）。比特率为1200比特/秒。4.1.1 调制器调制器接收由ITXD输入在NRZ形成的数字数据，并产生由OTXA输出的FSK调制信号。INRTS必须处于逻辑值的一个低值才能有效激发调制器。4.1.2 解调器解调器接收由IRXA输入的FSK信号并在线由ORXD输出的原始调制信号。正常的比特率为1200b/s。图4-2给出了解调过程。图 4-2 该解调器的信号时序图由于解调器的输出受限于载波检测信号，因此，只有IRXA信号足够大（通常为100mVp-p）才能被载波检测电路在ORXD产生的接收串行数据检测到。解调器的最大jitter为一比特的12%在HART规范的给定输入频率范围内，时钟频率为460.8kHz（+1%），零输入（IRXA）不对称。4.2 发射型号整形器发射信号整形器在OTAX产生符合HART的FSK调制信号。图4-3和图4-4 展示了A5191HRT的传送信号模式。由于IAREF=1.235VDC，OTXA 将有0.25至0.75VDC的电压浮动。 图 4-3 OTXA波形(1200Hz) 图 4-4 OTXA波形(2200Hz)4.3 载波检测电路图8显示出如果IRXAC电压低于ICDREF，载波检测比较器会产生逻辑低输出。比较器的输出被馈送到一个载波检测块。若INRTS是高值和比较器发出的4个连续脉冲相交，则载波检测块可引出载波检测输出引脚OCD的高值。只要INRTS位于高值而下一个比较器脉冲的接受少于2.5ms，OCD就会一直居高不下。一旦OCD不再活跃，比较器发出的4个连续脉冲会再一次激活OCD。4个连续脉冲的总值为3.33ms时接受的信号为1200HZ，总值为1.82ms时接收信号为2200Hz。4.4 模拟接收电路4.4.1 参考电压A5191HRT 需要两个参考电压， IAREF 和 ICDREF。IAREF设置了内部运算放大器和比较器的直流电路运作点。1.235VDC参考电压数（Analog Devices AD589）适合于IAREF。OCD（载波检测）变得活跃的数值是由直流电压差（ICDREF-IAREF）所决定的。选择0.08VCD电压差将载波检测设置到标称100 mVp-p。4.4.2 偏置电流电阻A5191HRT需要一个偏置电流电阻来连接OCBIAS和VSS。偏置电流控制内部运算放大器和比较器的工作参数。偏执电流的电阻值由IAREF参考电压和下面的公式所确定的：当IAREF为1.235VDC时，建议的偏置电流电阻500K。在图4-5中，除3M具有5的公差外，所有的外部电容量有5的公差，电阻的公差为1。在A5191HRT型外部，滤波器具有三极式和一极式，频率为624Hz高通滤波器和频率为2500Hz的低通过滤器。在内部，A5191HRT型拥有频率为35Hz的高通电极和频率为90kHz的低通电极。低通电极变化范围为30。整个滤波器的输入阻抗在频率低于50kHz时大于 150M。图 4-5 接收滤波器电路图4.5 振荡器A5191HRT需要一个位于OXTL频率为460.8kHz时钟信号。这个时钟信号由外部时钟或能够连接A5191HRT内部振荡器的外部部件来提供。4.5.1 内部振荡器的选择振荡器的电池可在频率为460.8kHz的晶体或陶瓷谐振器下发挥作用。并联谐振陶瓷谐振器连接于OXTL和IXTL之间。图4-6显示出为了时钟的生成晶体选择使用一个频率为460.8kHz的并联谐振晶体（容差为+1%）和两个调谐电容器。两个电容器的实际值可能是取决于制造商的建议。通常情况下，使用100pF470pF范围的电容器。4.5.2 外部时钟选择由于陶瓷谐振器的高成本和低使用性，从图4-7中可以看出一个频率为460.8khz的外部时钟相比于内部谐振器是更为需要的。而且，当使用外部时钟时，A5191HRT的电流消耗较少。当时钟与连接到VSS的OXTL和IXTL 连接时消耗的电流最小。图 4-6 晶体振荡器图 4-7 外部时钟振荡器