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单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,集成电路课程设计,7月1525日：集成电路课程设计,7月2628日：撰写课程设计报告,集成电路课程设计题目,1.DESIGN FLIP-FLOP,2.DESIGN A CMOS 8-BIT ALU,3.DESIGN A CMOS 8-BIT ACCUMULATOR,4.DESIGN A CMOS 8-BIT MULTIPLIER,5.DESIGN A 8-BIT BIDIRECTIONAL SHIFT REGISTER,6.DESIGN A SYNCHRONOUS 8-BIT UP AND DOWN COUNTER,1必做已做，26选作1个或自拟题目,集成电路课程设计,A Pseudo-Random Code Generator,8-bit binary divider,CRC(cyclic redundancy checker).,7x4 Signed Parallel Division Circuit,Automobile Locking Control System,Programmable counter,参考电路,DFF,ALU,FULL ADDER,N-BIT ADDER,MULTIPLIER,DFF,DFF,DFF,C,2,MOS,DFF,TSPC Register,ALU,4,4,4,4,4,AU,LU,MUX,A,B,F,0,1,S,C,-1,C,3,S,0,S,1,S,2,Full Adder,FULL ADDER SCHEMATIC,Complimentary Static CMOS Full Adder,FULL ADDER SCHEMATIC,The Mirror Adder,CMOS TG Full Adder Circuit,Sum,C,out,A,B,C,in,np-CMOS Adder Circuit,B,0,C,0,C,0,C,0,!C,1,!Sum,0,B,0,A,0,A,0,B,0,B,0,A,0,A,0,CLK,CLK,!CLK,!CLK,C,2,Sum,1,!A,1,!A,1,!B,1,!B,1,!A,1,!A,1,!B,1,!B,1,!C,1,!C,1,!CLK,!CLK,CLK,CLK,1,x,0,x,0,x,1,x,0,x,0,x,1,x,1,x,N-bit Adder,The Ripple-Carry Adder,N-bit Adder,超前进位加法器进位逻辑,N-bit Adder,Ripple-Carry Adder,LookAhead,Carry-Bypass Adder,Carry-Select Adder,MULTIPLIER,The Array Multiplier,MULTIPLIER,Carry-Save Multiplier,How to Get Started,Find relevant reading materials.,Develop a set of specifications that meet the requirements of the chosen application,Make a high level rough sketch,Divide and conquer,Make a schedule and stick to it,课程设计报告要求,摘要,选题意义、背景，根本理论，方案选择,设计详细内容,ASIC设计流程,代码描述及仿真向量,仿真验证Verilog XL 或 NC-lanch,逻辑综合,布局布线,幅员生成,DRC，EXTRACT，LVS,定制设计流程,电路原理及电路设计,电路仿真验证Verilog XL 或 NC-lanch,幅员设计,DRC，EXTRACT，LVS,最高工作频率分析,结论功能、面积、功耗、延时,Some Final Tips,Start early;dont leave anything until last minute.,Periodically save backups.,Keep track of what needs to be turned in as you go along.,Some Design Tips,Make everything modular,and test often,at every step.,Try to keep everything a standard rectangular shape,including final design.,Using Euler paths to create efficient layouts for complex gates is better than stringing together many simple gates.,Always keep in mind big picture.,How am I going to route inputs/power to each block in the final layout?,Use wide Vdd and Gnd lines,route these lines(and others,like clock)efficiently.,Dont route poly over a long distance.,
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