第七章半导体存储器1

第七章,7.1,概述,7.3,只读存储器（,ROM,）,7.2,随机存取存储器（,RAM,）,下一页,前一,页,退出,7.1,概述,下一页,前一,页,退出,半导体存储器,RAM,ROM,双极型,MOS,型,动态,静态,掩膜,ROM,PROM,EPROM,EEPROM,FLASH,一半导体存储器的分类,二半导体存储器的主要技术指标,1,、存储容量,2,、存取时间,7.2,随机存取存储器（,RAM,）,一静态,RAM,1,静态,RAM,的内部结构,2,静态,RAM,的外部特性（引脚图）,A,0,A,N,1,D,0,D,n,CE,OE,WR,RAM,引脚分为,3,个部分，,AB,、,DB,、,CB,（,1,）,AB,总线,AB,总线的宽度决定了存储单元数的多少,W=2,N,存储单元数,A,0,A,N,1,D,0,D,n,CE,OE,WR,（,2,）,DB,总线,DB,总线的宽度决定了每个存储单元位数的多少。,（,3,）,CB,总线,每片,RAM,通常有下列几条控制线,CE,：,片选线，当其有效，该芯片被选中。,OE,：,读线，当其有效，读操作。,WR,：,写线，当其有效，写操作。,8,条数据线，每字长度为,8,位,13,条地址线，存储字数为：,2,13,8,3,、,RAM,集成芯片,6264,简介,6264,外引线排列图,WR,NC,GND,15,14,16,13,17,12,18,11,19,10,20,9,21,8,22,7,23,6,24,5,25,4,26,3,27,2,28,1,A,12,A,7,A,6,A,5,A,4,A,3,A,2,A,1,A,0,I/O,0,I/O,1,I/O,2,V,DD,CS,2,A,8,A,9,A,11,OE,A,10,CS,1,I/O,7,I/O,6,I/O,5,I/O,4,I/O,3,HM,6264,6264,工作状态,高阻,高阻,高阻,输入数据,输出数据,I/O,1,1,1,0,输出禁止,0,维持（未选中）,1,维持（未选中）,0,1,0,写（选中）,1,0,1,0,读（选中）,WR,OE,CS,2,CS,1,工作状态,4,、其他常见静态,RAM,集成芯片,D,0,D,7,A,0,A,13,CS,OE,WR,62128,D,0,D,7,A,0,A,14,CS,OE,WR,62256,D,0,D,7,A,0,A,10,CS,OE,WR,6116,三、静态,RAM,与,CPU,的连接,1,、,CPU,与存储器连接有关的引脚,地址总线：,AB,数据总线：,DB,控制总线：,CB,主要有：,RD,、,WE,、,READY,8086/8088,为,20,条地址线，,A,0,A,19,8086/8088,为,8,条数据线，,D,0,D,7,2,、地址编码,8086/8088,的,20,条地址线,A,0,A,19,，可以有,2,20,不同编码，用于选择不同的存储单元。,3,、连接实例,用,62128,组成,32K,的存储器，首地址为,00000H,D,0,D,7,A,0,A,13,OE,WR,CE,1#,D,0,D,7,A,0,A,13,OE,WR,CE,2#,CPU,D,7,D,0,A,13,A,0,A,14,A,15,A,19,RD,WE,译,码,器,用,62128,组成,32K,的存储器，首地址为,00000H,线译码,部分地址译码,D,0,D,7,A,0,A,13,OE,WR,CE,1#,D,0,D,7,A,0,A,13,OE,WR,CE,2#,A,14,特点：译码电路简单；同一存储单元，地址不唯一。,用,62128,组成,32K,的存储器，首地址为,00000H,全译码,全部地址线参与译码译码,D,0,D,7,A,0,A,13,OE,WR,CE,1#,D,0,D,7,A,0,A,13,OE,WR,CE,2#,特点：译码电路复杂；同一存储单元，地址唯一。,A,14,A,17,74LS,138,Y,0,Y,1,Y,7,A,B,C,S,2,S,0,S,A,15,A,16,A,18,A,19,A,18,A,17,A,16,A,15,A,14,A,13,A,0,片内,0 0 0 0 0 0 0 0,A,19,位扩展,D,15,D,9,D,8,D,7,D,1,D,0,1,1,WR,CS,1,A,0,A,12,适用于字数够用，但每字的位数（字长）不够的情况。,如：,8K8 8K16,I/O,7,I/O,1,I/O,0,OE,WR,A,12,A,0,CS,1,CS,2,I/O,7,I/O,1,I/O,0,OE,WR,A,12,A,0,CS,1,CS,2,6264 ,6264 ,7.3,只读存取存储器（,ROM,）,一,EPROM,的结构,1,、,EPROM,的内部结构,2,、,EPROM,的引脚功能,EPROM,引脚分为,3,个部分，,AB,、,DB,、,CB,每片,EPROM,通常有下列几条控制线,CE,：,片选线，当其有效，该芯片被选中。,OE,：,读线，当其有效，读操作。,写入所需高电压，当,EPROM,写入时，此脚一般接,25V,电源。,V,P,：,PGM:,编程脉冲,A,0,A,N,1,D,0,D,n,CE,OE,V,P,PGM,二,EPROM,芯片举例,A,7,A,6,A,5,A,4,A,3,A,2,A,1,A,0,O,1,O,2,O,3,GND,U,CC,A,8,A,9,U,PP,OE,A,10,CE/PGM,O,7,O,6,O,5,O,4,O,3,1,2,3,4,5,6,7,8,9,10,11,12,24,23,22,21,20,19,18,17,16,15,14,13,1,、,2716,1,）,11,条地址线,2,）,8,位数据线,3,）,3,条控制线,U,PP,、,CE/PGM,、,OE,CE/PGM,OE,U,PP,D,0,D,7,读,0,0,5V,数据输出,读禁止,1,5V,高阻,维持（备用）,1,5V,高阻,编程（写入）,50ms,脉冲,1,25V,数据输入,编程校验,0,0,25V,数据输出,编程禁止,0,1,25V,高阻,2,、,2764,1,）,12,条地址线,2,）,8,位数据线,3,）,4,条控制线,U,PP,、,CE,、,PGM,、,OE,CE PGM,OE,U,PP,D,0,D,7,读,0 1,0,5V,数据输出,读禁止,1,5V,高阻,维持（备用）,1 ,5V,高阻,三利用,ROM,实现组合逻辑函数,实现方法：,列出函数的真值表，将函数结果存入存储单元，地址线作为输入变量，从数据线读的数据既是函数结果。,例：用,ROM,实现以下函数,A,1,A,0,D,3,D,2,D,1,D,0,1 0 1 0,1 1 0 1,0 1 0 1,0 0 1 1,7.4,MCS-51,单片机的存储器扩展,一、,51CPU,与存储器连接的有关引脚,1,、,P0.0P0.7,2,、,P2.0P2.7,：,3,、,控制线：,AD,0,AD,7,分时作为低,8,位地址总线和,8,为数据,线,A,8,A,15,高,8,位地址线,1,）,ALE/PROG,、,ALE,：地址锁存有效信号,PROG,编程脉冲输入端,2,）,PESN,片外程序存储器的读选信号,3,）,EA/VPP,VPP,编程电源电压,EA:0,选用外部程序存储器,EA:1,选用内部程序存储器,4,）,WR,5,）,RD,片外数据存储器写选通信号,片外数据存储器读选通信号,二、,51,单片机的存储器结构,0FFFFH,1000H,ROM,0FFFFH,0000H,RAM,片外,RAM,片内,RAM,00FFH,0000H,外部,EA=0,0FFFH,0000H,片内,EA=1,0FFFH,0000H,MOVX,RD WR,有效,MOV,PESN,有效,三、,EPROM,的扩展,用,27256,扩展,64K,外部程序存储器,D,0,D,7,OE,LE,Q,0,Q,7,A,0,A,7,CPU,P0.0,A,8,ALE,EA,P0.7,P2.0,P2.6,P2.7,A,14,A,15,RD,PESN,WE,D,0,D,7,A,0,A,14,OE,CE,1#,A,8,A,7,VPP,。,D,0,D,7,A,0,A,14,OE,CE,2#,A,8,A,7,VPP,74LS373,5V,5V,四、,SRAM,的扩展,四、,SRAM,的扩展,用,62256,扩展,64K,外部数据存储器,D,0,D,7,OE,LE,Q,0,Q,7,A,0,A,7,CPU,P0.0,A,8,ALE,EA,P0.7,P2.0,P2.6,P2.7,A,14,A,15,RD,PESN,WE,D,0,D,7,A,0,A,14,OE,CE,1#,A,8,A,7,WE,。,D,0,D,7,A,0,A,14,OE,CE,2#,A,8,A,7,WE,74LS373,1,、常用的,E2PROM,芯片,五、,EEPROM,的扩展,