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Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,54,网络与分布式系统研究室(,DisNet Lab of NWU),2024/9/17,Computer Operating Systems,FANG Dingyi(,Department of Networking & Communication Eng.,TEL: 88308273(lab); 88308114(O),Email:,销售信,1,Words before the Course:,Textbook,:,Operating SystemsInternals and Design,Principles,(3,ird,or 4,th,edition),，,William Stalling, Prentice Hall/,清华大学出版社,;,魏迎梅等译，电子工业出版社出版,2,Words before the Course:,Grade:,30%(10%presentation+10%homewwork+10%project),+,30%(mid term exam) +,40%(final exam),Claim of the exam,:,all question are in English,3,Words before the Course:,Reference boobs,（,in Chinese,）,:,1.,计算机操作系统,骆斌等著，高等教育出版社；,2.,计算机操作系统,孙雅如、房鼎益著，西电出版社；,3.,计算机操作系统,汤子赢等著，西电出版社；,4.,计算机操作系统,何炎祥等著，清华大学出版社；,4,Computer System Overview,Chapter 1,5,Operating System,Exploits the hardware resources of one or more processors,(,充分利用处理机资源,),Provides a set of services to system users,(,提供方便用户使用的服务,),Manages secondary memory and I/O devices,(,管理外存与外设,),Basic Elements,Processor,Main Memory,referred to as real memory or primary memory,Volatile,(,易挥发的,掉电后内容丢失,),I/O modules,secondary memory devices,communications equipment,terminals,System bus,communication among processors, memory, and I/O modules,Top-Level Components,Processor Registers,User-visible registers,Enable programmer to minimize main-memory references by optimizing register use,Control and status registers,Used by processor to control operating of the processor,Used by operating-system routines to control the execution of programs,User-Visible Registers,May be referenced by machine language,Available to all programs - application programs and system programs,Types of registers,Data,Address,Index,Segment pointer,Stack pointer,User-Visible Registers,Address Registers,Index,involves adding an index to a base value to get an address,Segment pointer,when memory is divided into segments, memory is referenced by a segment and an offset,Stack pointer,points to top of stack,Control and Status Registers,Program Counter (PC),Contains the address of an instruction to be fetched,Instruction Register (IR),Contains the instruction most recently fetched,Program Status Word (PSW),condition codes,Interrupt enable/disable,Supervisor/user mode,Control and Status Registers,Condition Codes or Flags,Bits set by the processor hardware as a result of operations,Can be,access,ed by a program but not,alter,ed,Examples,positive result,negative result,zero,Overflow,Instruction Execution,Two steps,Processor reads instructions from memory,Fetches,Processor executes each instruction,Instruction Cycle,Instruction Fetch and Execute,The processor fetches the instruction from memory,Program counter (PC) holds address of the instruction to be fetched next,Program counter is incremented after each fetch,Instruction Register,Fetched instruction is placed in the instruction register,Types of instructions,Processor-memory,transfer data between processor and memory,Processor-I/O,data transferred to or from a peripheral device,Data processing,arithmetic or logic operation on data,Control,alter sequence of execution,Characteristics of a Hypothetical Machine,Example of Program Execution,Direct Memory Access (DMA),I/O exchanges occur directly with memory,Processor grants I/O module authority to read from or write to memory,Relieves the processor responsibility for the exchange,Processor is free to do other things,Interrupts,An interruption of the normal sequence of execution,Improves processing efficiency,Allows the processor to execute other instructions while an I/O operation is in progress,A suspension of a process caused by an event external to that process and performed in such a way that the process can be resumed,Classes of Interrupts,Program Flow of Control Without Interrupts,Program Flow of Control With Interrupts, Short I/O Wait,Program Flow of Control With Interrupts; Long I/O Wait,Interrupt Handler,A program that determines nature of the interrupt and performs whatever actions are needed,Control is transferred to this program,Generally part of the operating system,Interrupts,Suspends the normal sequence of execution,Interrupt Cycle,Interrupt Cycle,Processor checks for interrupts,If no interrupts fetch the next instruction for the current program,If an interrupt is pending,(,待解决的,),suspend execution of the current program, and execute the interrupt-handler routine,Timing Diagram Based on Short I/O Wait,Timing Diagram Based on Short I/O Wait,Simple Interrupt Processing,Changes in Memory and Registers for an Interrupt,Changes in Memory and Registers for an Interrupt,Multiple Interrupts,Disable interrupts while an interrupt is being processed,Multiple Interrupts,Define priorities for interrupts,Multiple Interrupts,Multiprogramming,Processor has more than one program to execute,The,sequence,the programs are executed depend on their relative priority and whether they are waiting for I/O,After an interrupt handler completes, control may not return to the program that was executing at the time of the interrupt,Memory Hierarchy,Faster access time, greater cost per bit,Greater capacity, smaller cost per bit,Greater capacity, slower access speed,Memory Hierarchy,Going Down the Hierarchy,Decreasing cost per bit,Increasing capacity,Increasing access time,Decreasing frequency of access of the memory by the processor,Locality of reference,Secondary Memory,Nonvolatile,Auxiliary memory,Used to store program and data files,Disk Cache,A portion of main memory used as a buffer to temporarily to hold data for the disk,Disk writes are clustered,Some data written out may be referenced again. The data are retrieved rapidly from the software cache instead of slowly from disk,Cache Memory,Invisible to operating system,Increase the speed of memory,Processor speed is faster than memory speed,Exploit the principle of locality,Cache Memory,Cache Memory,Contains a copy of a portion of main memory,Processor first checks cache,If not found in cache, the block of memory containing the needed information is moved to the cache and delivered to the processor,Cache/Main Memory System,Cache Read Operation,Cache Design,Cache size,Small caches have a significant impact on performance,Block size,The unit of data exchanged between cache and main memory,Larger block size more hits until probability of using newly fetched data becomes less than the probability of reusing data that have to be moved out of cache,Cache Design,Mapping function,Determines which cache location the block will occupy,Replacement algorithm,Determines which block to replace,Least-Recently-Used (LRU) algorithm,Cache Design,Write policy,When the memory write operation takes place,Can occur every time block is updated,Can occur only when block is replaced,Minimizes memory write operations,Leaves main memory in an obsolete state,Programmed I/O,I/O module performs the action, not the processor,Sets appropriate bits in the I/O status register,No interrupts occur,Processor checks status until operation is complete,Interrupt-Driven I/O,Processor is interrupted when I/O module ready to exchange data,Processor saves context of program executing and begins executing interrupt-handler,No needless waiting,Consumes a lot of processor time because every word read or written passes through the processor,Direct Memory Access,Transfers a block of data directly to or from memory,An interrupt is sent when the transfer is complete,Processor continues with other work,
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