资源描述
Deog-Kyoon JeongSeoul National UniversityHigh-Speed Serial Link1Deog-Kyoon JeongHigh-Speed SerIntroductionHigh-speed I/O overviewHot design issuesDesign examplesSummaryOutline2IntroductionOutline2IntroductionMoores lawPerformance&density improvement in digital system1001011021031041051061071081980198419881992199620002004Gates density1001011021031041980198419881992199620002004CPU performance3IntroductionMoores law1001011IntroductionMoores law1001011021031041980198419881992199620002004CPU performanceMemory access1001011021031041051061071081980198419881992199620002004Gates densitySignal pinsGrowing gap limits system performance!4IntroductionMoores law1001011Digital System PerformanceCommunication-boundComputation-boundPerformance bottleneckThe cost of arithmetic operation is cheap now“Pentium Pro”10 20 cycles/Arithmetic operation70 cycles/DRAM access“Pentium 4”20 30 cycles/Arithmetic operation500 600 cycles/DRAM access5Digital System PerformanceCommComputing SystemHigh-speed I/O is needed everywhereNorthBridgeCPUSouthBridgeMemoryGraphicDiskLANDisplaySwitchLocal I/OLong distanceSAN6Computing SystemHigh-speed I/OParallel Bus&Serial LinkGroup data(Bus)Source synchronousMatched traceParallel BusCoreI/OClockDataCoreI/OSerial LinkCoreI/OSerialDataCoreI/OSingle tracePlesiochronousClock embedded in dataClock&data recovery7Parallel Bus&Serial LinkGrouParallel vs.SerialParallel BusSerial LinkHardware ComplexityLowHighLatencyShortLongSpeed 200Mbps/pin 10Gbps/pinor moreManufacturingCostHighLowWorld is moving toward“serial link”or“serial-link-like parallel bus”!8Parallel vs.SerialParallel BuSerial Link ArchitectureReceiverTransmitterPLLFramerPCSSerializerDeframerClock recoveryChannelPCSDeserializerTransmitter+Receiver=Transceiver9Serial Link ArchitectureReceivLink ComponentPhaseDetectorLoop-FilterVoltage-ControlledOscillator MCKi(fin)VctrerrorCKo(fout)Phase-locked Loop(PLL)Frequency multiplication:fout=MfinJitter filterZero-delay buffer10Link ComponentPhaseLoop-VoltagLink ComponentHigh-speed,low voltage swing interfaceUsually,differentialSmall swing-several hundreds mVZ0Z0ChannelDC blockTermination(R=Z0)VTTVRRToCDRDriverLimiting amp11Link ComponentHigh-speed,low Link ComponentClock&data recovery(CDR)circuitsNRZ PhaseDetectorLoop-FilterVoltage-ControlledOscillatorDiVctrerrorDoCKrDecision circuitDiDoCKr0110100100012Link ComponentClock&data recLink Performance MetricEye diagram&jitterRandom bit sequenceTbitEye diagramTbitTiming uncertainty:JitterJitter histogramIdealRealistic13Link Performance MetricEye diaLink Performance MetricEye diagram example Near end&far endPLLFramerDeframerClock recoveryChannel14Link Performance MetricEye diaLink Performance MetricBit-error rate(BER)In most serial link standards,BER 10-12 is specifiedEye diagramJitter histogramRecovered clockBit error!Jitter PDF=f(x)15Link Performance MetricBit-errHigh-Speed Link StandardsNorthBridgeCPUSouthBridgeMemoryGraphicDiskLANDisplaySwitchLocal I/OSANDVILVDSEthernetSATASONET/SDHFibreChannelInfiniBandPCI ExpressHyperTransportRDRAMXDR16High-Speed Link StandardsNorthIndustry Roadmaps0.1G1G10G100GData-rateEthernetSONET/SDHFast Ethernet Gigabit Ethernet 10G EthernetOC-48 OC-192OC-768SATAOC-12XAUIGen1Gen2Gen3PCI ExpressPCIe1.0PCIe2.0(?)Fibre ChannelFC-PI-1FC-PI-2 10GFCDVIVGAUXGASXGAYear 2005,world is here!17Industry Roadmaps0.1G1G10G100GDigital Visual Interface(DVI)PC display CRT(analog)LCD(digital)DVI Digital Visual InterfaceAnalogDigital18Digital Visual Interface(DVI)Digital Visual Interface(DVI)TMDSTransition minimized differential signalingEMI reductionTMDSencoderPLLGraphiccontrollerTMDSdecoderPLLDisplaycontroller19Digital Visual Interface(DVI)High Definition Multimedia Interface(HDMI)HDMIHigh-definition multi-media interfaceDigital video+multi-channel audio interface for consumer electronicsCompatible with DVI20High Definition Multimedia IntSerial ATA(SATA)Next generation ATA bus within PC boxEliminates fat ATA cablesPoint-to-point connection 1.5G/3G/6GParallel ATA cablingSerial ATA cabling21Serial ATA(SATA)Next generatiTransceiver Chip DesignTechnologyCMOS,InP,GaAs,SiGe,BiCMOS CMOS will be the eventual winner Low cost,high-integritySpeedPower consumptionAreaLevel of integrationMixed-signal SoC Serial link interface+digital circuitryTrade-off!22Transceiver Chip DesignTechnolHot Design IssuesPLLFramerDeframerClock recoveryCMOS serial link transceiver23Hot Design IssuesPLLFramerDefrHot Design IssuesPLLFramerDeframerClock recoveryCMOS serial link transceiverPrecise-timing generation-High-frequency,low jitter PLLHigh-performance CDR-High-speed NRZ PD-Various CDR architecturesHigh-speed CMOS circuits-Logic gates,analog bufferChannel loss compensation-Equalizer24Hot Design IssuesPLLFramerDefrPrecise Timing generationVCO noise PLL jitter Data eye jitterLow noise,high-frequency VCO is requiredPhaseDetectorLoop-FilterVoltage-ControlledOscillator MCKi(fin)VctrerrorCKo(fout)25Precise Timing generationVCO nVoltage-Controlled OscillatorPoorNoiseGoodLowFrequencyHighWideTuning rangeNarrowLowCostHighRing oscillatorM stagesdMTf21=Td =C V/ILC tank oscillatorParasitic resistanceNegative gmOn-chip spiral LOn-chip varactorvarLCfp p21=26Voltage-Controlled OscillatorPHigh-Speed CMOS CircuitsCurrent-mode logic(CML)ZLNMOSLogic R R+L R+T-coilCMOS logicNMOSPull-downPMOSPull-upComplementaryIntermediateSpeedFastSmallAreaLargeSmallPower consumptionLargeHigh-speed logic gates27High-Speed CMOS CircuitsCurrenHigh-Speed CMOS CircuitsHigh-speed buffer with on-chip inductorShunt peaking Inserts a zero at high frequencySeries peaking Isolates the buffer output node from load capacitanceNormalShunt peakingShunt peakingShunt seriespeakingSeries peakingShunt double-series peakingSeries peaking28High-Speed CMOS CircuitsHigh-sHigh-Speed CDR NRZ PDHogge phase-detector Linear PDFull-rate operationMatched up/down when locked Less noisyD QD QDNUPCKDABDCKABUPDNArea difference Phase errorVery short pulse!Phase error Clock early29High-Speed CDR NRZ PDHogge pHigh-Speed CDR NRZ PDAlexander phase-detector Binary PDWith multi-phase clock Time interleavingBang-bang control Noisy D0D1ABTClock earlyD0D1ABTClock lateUPDND QD QD QD QBADNUPTCKD30High-Speed CDR NRZ PDAlexandHigh-Speed CDR ArchitecturesPLL-based CDR1 PLL/channel Precise phase controlSuitable for high-speed,high-performance systemNRZ PhaseDetectorLoop-FilterVoltage-ControlledOscillatorDiVctrerrorDoCKrDecision circuitEither linear or binary31High-Speed CDR ArchitecturesChannel LossBand-limited channelBonding wire,PCB trace,connector,cable Skin effectDielectric loss32Channel LossBand-limited channChannel Loss EffectInter-symbol interference(ISI)00010111Time-4TB-3TB-2TB-TBTB2TB3TB4TB0Amplitude33Channel Loss EffectInter-symboChannel Loss CompensationTX Pre-emphasisWithpre-emphasisWithoutpre-emphasis34Channel Loss CompensationTX Channel Loss CompensationRX Equalization Continuous time equalizergDinDoutHigh-pass filterCapacitivedegeneration35Channel Loss CompensationRX Design Examples40Gbps transmitterProcess 0.13 CMOSPower 2.8WArea 2.5 3.6 mm2Features20G standing-wave VCOShunt-double series peaking at 10/20/40G buffersActive feedback at 20G divider410 on-chip spiral inductors36Design Examples40Gbps transmitDesign Examples40G transmitter Standing wave VCOVaractors37Design Examples40G transmitterDesign Examples40G transmitter test resultsTest chip25ps38Design Examples40G transmitterDesign ExamplesFeatures10G LC-tank VCOPLL-based 10G CDRDLL-based quad 3.125G CDR(XAUI)Integrated with digital control core10G Ethernet PHY with XAUI interfaceProcess 0.13 CMOSPower 900mWArea 5 5 mm239Design ExamplesFeatures10G EthDesign Examples3.5G continuous time adaptive equalizerProcess 0.18 CMOSArea 0.48 0.73 mm2Power 80mW 3.5GCable inputCable outputEqualizer outputFeatures 3.5G Adaptive mode 5G Manual mode40Design Examples3.5G continuousSummaryNow,digital system performance is bounded by system I/O bandwidthIn industry,serial link I/O is going mainstreamToward low-cost,high-bandwidth system I/O,we should overcome several physical limitations such asJitter&noise Channel lossDevice speed41SummaryNow,digital system per
展开阅读全文