时序电路的基本概念课件

Digital Integrated Circuits2ndSequential CircuitsDigital Integrated CircuitsA Design PerspectiveDesigning SequentialLogic CircuitsJan M.RabaeyAnantha ChandrakasanBorivoje Nikolic Digital Integrated Circuits2ndSequential Circuits第第7章章 时序电路设计时序电路设计一、时序电路的基本概念一、时序电路的基本概念二、二、Latches（锁存器）（锁存器）三、三、Flip-flops（触发器）（触发器）四、四、Design of Sequential machines Digital Integrated Circuits2ndSequential CircuitsSequential Logic2 storage mechanismspositive feedback一、时序电路的基本概念一、时序电路的基本概念charge-based Digital Integrated Circuits2ndSequential Circuits1、Latches and Flip-flopsLatches：对Latches赋值后，存贮值立即输出（基本、同步触发器）Flip-flops：对Flip-flops赋值后，存贮值不立即输出，当时钟边沿时输出存贮值（边沿触发器）nLatch:transparentwheninternalmemoryisbeingsetfrominput.nFlip-flop:nottransparentreadinginputandchangingoutputareseparateevents.Digital Integrated Circuits2ndSequential CircuitsqIn our text:a latch is level sensitive a register is edge-triggeredqThere are many different naming conventionsFor instance,many books call edge-triggered elements flip-flopsThis leads to confusion however Digital Integrated Circuits2ndSequential CircuitsLatch versus RegisterqLatchstores data when clock is low DClkQDClkQqRegisterstores data when clock rises ClkClkDDQQ Digital Integrated Circuits2ndSequential CircuitsLatches Digital Integrated Circuits2ndSequential Circuits2、动态与静态、动态与静态Dynamic(charge-based):用寄生电容存数据Static:用反相器feedback存数据 Digital Integrated Circuits2ndSequential CircuitsnD-typenT-typenSR-typenJK-type3、功能、功能按功能分类：按功能分类：Digital Integrated Circuits2ndSequential Circuits（1 1）RSRS触发器触发器触发器触发器S RQn+1 0 0 0 1 1 0 1 1Qn01不定1)、特性表、特性表2)、函数式（状态方程）、函数式（状态方程）Digital Integrated Circuits2ndSequential Circuits（2 2）JKJK触发器触发器触发器触发器CP J KQn+1 X X X 0 0 0 1 1 0 1 1Qn Qn01Qn Digital Integrated Circuits2ndSequential CircuitsCPC11DD（3 3）D D触发器触发器触发器触发器 CP DQn+1 0 X 1 0 1 1Qn 01 Digital Integrated Circuits2ndSequential Circuits二、二、Latches（锁存器）（锁存器）1、Dynamic Latches(动态锁存器动态锁存器)(1)(1)基于传输门的基于传输门的基于传输门的基于传输门的Dynamic Dynamic LatchesLatchesCg:存贮节点的寄生电容主要由反相器的栅电容组成存贮节点 Digital Integrated Circuits2ndSequential Circuits1）Operation=1:？=0:？n=0:transmissiongateisoff,inverteroutputisdeterminedbystoragenode.n=1:transmissiongateison,inverteroutputfollowsDinput.Digital Integrated Circuits2ndSequential Circuits2）Layout3）特点电路简点动态电容会放电 Digital Integrated Circuits2ndSequential Circuits(2)(2)ClockedClocked CMOS LatchesCMOS Latches 钟控钟控钟控钟控CMOSCMOS锁存器锁存器锁存器锁存器Q存贮节点(D)=1:？=0:？特点电路简点动态电容会放电Operation(C2MOSLatches)Digital Integrated Circuits2ndSequential CircuitsClocked inverter operationq=0:both clocked transistors are off,output is floating.q=1:both clocked inverters are on,acts as an inverter to drive output.symbolcircuit Digital Integrated Circuits2ndSequential Circuits(3)(3)Quasi-staticQuasi-static LatchesLatches 准静态锁存器准静态锁存器准静态锁存器准静态锁存器LD=0:Q存贮2=0:正反馈断开，电路成动态LatchOperationLD=1:Q=D存贮节点2=1:存贮节点形成正反馈，电路成静态锁存器(D)Q Digital Integrated Circuits2ndSequential Circuits（4 4）TSPCTSPCNegativelatch(transparentwhenCLK=0)Positivelatch(transparentwhenCLK=1)Digital Integrated Circuits2ndSequential CircuitsIncluding Logic in TSPCANDlatchExample:logicinsidethelatch Digital Integrated Circuits2ndSequential Circuits2、Static Latches(静态锁存器静态锁存器)(1)基于传输门的静态锁存器基于传输门的静态锁存器基于传输门的静态锁存器基于传输门的静态锁存器 Static transmission-gate latch Static transmission-gate latch=0:Q=D=1:Q保持bQbQDb Digital Integrated Circuits2ndSequential Circuits(2)(2)基于静态基于静态基于静态基于静态CMOSCMOS门的锁存器门的锁存器门的锁存器门的锁存器 Static latch based on simple Static latch based on simple gategateNOR-basedset-reset Digital Integrated Circuits2ndSequential CircuitsCross-coupledNANDsAddedclockThisisnotusedindatapathsanymore,butisabasicbuildingmemorycellCross-Coupled NAND Digital Integrated Circuits2ndSequential Circuits(3)(3)MuxMux-Based Latches-Based Latches 基于选择器的锁存器基于选择器的锁存器基于选择器的锁存器基于选择器的锁存器Negative latch(transparent when CLK=0)Positive latch(transparent when CLK=1)CLK10DQ0CLK1DQ Digital Integrated Circuits2ndSequential Circuits0CLK1DQ Digital Integrated Circuits2ndSequential Circuits(4)(4)Static Latch based on Static Latch based on RAMRAMDQbQDb Digital Integrated Circuits2ndSequential CircuitsDQbQDbM1M2M3M4QM5DM6CLKM7DbM8CLKVDDQ Digital Integrated Circuits2ndSequential Circuits（5 5）其它逻辑功能的锁存器）其它逻辑功能的锁存器）其它逻辑功能的锁存器）其它逻辑功能的锁存器 (以静态为例）以静态为例）以静态为例）以静态为例）1）加Set和Reset端（异步）（1）基于传输门bQbQDb Digital Integrated Circuits2ndSequential Circuits（2）StaticLatchbasedonRAMDQbQDb Digital Integrated Circuits2ndSequential Circuits2）改为T-typeLatchDQbQDb Digital Integrated Circuits2ndSequential Circuits 三、三、Flip-flopsqNot transparentuse multiple storage elements to isolate output from input对Flip-flops赋值后，存贮值不立即输出，当时钟边沿时输出存贮值Majorvarieties:master-slave;主从结构edge-triggered.边沿触发 Digital Integrated Circuits2ndSequential CircuitsMaster-slave flip-flopDQmasterslaveq=0:master latch is disabled;slave latch is enabled,but master latch output is stable,so output does not change.q=1:master latch is enabled,loading value from input;slave latch is disabled,maintaining old output value.Master-slaveoperation：Digital Integrated Circuits2ndSequential Circuits1、Dynamic flip-flops (动态触发器动态触发器)(1)(1)基于传输门的基于传输门的基于传输门的基于传输门的Dynamic flip-flopsDynamic flip-flops这是上边沿masterslaveb=0：赋值=1：内部Q保存，slave输出改变内部的Q Digital Integrated Circuits2ndSequential Circuits（）（）（）（）C C2 2MOSMOS这是上边沿 Digital Integrated Circuits2ndSequential Circuits（）（）（）（）TSPC RegisterTSPC Register这是上边沿 Digital Integrated Circuits2ndSequential Circuits2、Static flip-flops(静态触发器静态触发器)(1)基于传输门的静态触发器基于传输门的静态触发器基于传输门的静态触发器基于传输门的静态触发器这是上边沿 Digital Integrated Circuits2ndSequential Circuits（）（）（）（）Master-Slave(Edge-Triggered)Master-Slave(Edge-Triggered)RegisterRegister这是上边沿 Digital Integrated Circuits2ndSequential CircuitsDQbQDb()Static flip-flops based on RAMStatic flip-flops based on RAMbDQbQDb这是下边沿 Digital Integrated Circuits2ndSequential Circuits四、四、Design of Sequential machines1、FSM2、设计方法与特点、设计方法与特点3、设计实例、设计实例 Digital Integrated Circuits2ndSequential Circuits1、FSM structureFSM-finitestatemachine有限状态机输入输入输出输出状态状态信号信号驱动（激励信号)1 1）FSM structureFSM structure Digital Integrated Circuits2ndSequential Circuits、输出方程、输出方程2、驱动方程、驱动方程组合逻辑组合逻辑3、状态方程、状态方程XYQD2 2）FSMFSM三个基本方程三个基本方程三个基本方程三个基本方程触发器特性方程触发器特性方程 Digital Integrated Circuits2ndSequential Circuits设计的一般步骤设计的一般步骤1、确定输入变量、输出变量、状态、确定输入变量、输出变量、状态 （通过分析问题）（通过分析问题）2、作出状态图、作出状态图 （根据问题含义）（根据问题含义）3、状态简化。即消除冗余状态。、状态简化。即消除冗余状态。4、确定状态编码，画出卡诺图、确定状态编码，画出卡诺图5、写出三个方程；选定触发器，写出触发器的激励函数、写出三个方程；选定触发器，写出触发器的激励函数6、画出逻辑电路图、画出逻辑电路图7、电路用触发器电路用触发器(D,JK)和与非门和与非门（用（用CMOS晶体管级，版图实现晶体管级，版图实现)设计要求：完成给定的功能设计要求：完成给定的功能2、设计方法与特点、设计方法与特点与数电相同与数电相同 Digital Integrated Circuits2ndSequential CircuitsQ3Q2Q1Q0Y000000010010010101100111100000000001001001001000113、设计实例、设计实例十进制计数器为例实验内容PSPICE可选1 1）状态图）状态图）状态图）状态图 Digital Integrated Circuits2ndSequential Circuits23QQ01QQ00000111100111100000000110+3Q23QQ01QQ00000111100111100000011011+2Q23QQ01QQ00000111100111100000011011+1Q23QQ01QQ00000111100111100000011111+0Q2 2）卡诺图）卡诺图）卡诺图）卡诺图 Q3Q2Q1Q0Y00000001001001010110011110000000000100100100100011 Digital Integrated Circuits2ndSequential Circuits23QQ01QQ00000111100111100000000110+3Q23QQ01QQ00000111100111100000011011+2Q23QQ01QQ00000111100111100000011011+1Q23QQ01QQ00000111100111100000011111+0Q3 3）驱动方程）驱动方程）驱动方程）驱动方程 Digital Integrated Circuits2ndSequential CircuitsD0Q0Q0D1Q1Q1D2Q2Q2D3Q3Q3Q0clk4 4）门级电路图）门级电路图）门级电路图）门级电路图Q0Q1Q2Q3Q0Q2Q1Q0Q1Q0Q1Q0Q2 Digital Integrated Circuits2ndSequential Circuits5 5）晶体管级电路图）晶体管级电路图）晶体管级电路图）晶体管级电路图 D0Q0Q0D1Q1Q1D2Q2Q2D3Q3Q3Q0clkQ0Q1Q2Q3Q0Q2Q1Q0Q1Q0Q1Q0Q2(1)、D触发器(2)、与非门（二输入，三输入）(3)、异或门（二输入）Digital Integrated Circuits2ndSequential Circuits基于CMOS传输门的下边沿D触发器(1)、D触发器高电平输入型锁存器低电平输入型锁存器 Digital Integrated Circuits2ndSequential Circuits(2)、与非门（二输入，三输入）(3)、异或门（二输入）