Cyclone II器件中文资料

一、外文资料译文：Cyclone II 器件系列简介关键词：cyclone II器件；特点；简介；在非常成功的第一代Cyclone器件系列之后，Altera的Cyclone II FPGA系列扩大低 成本的FPGA的密度，最多达68，416个逻辑单元（LE），提供622个可用的输入/输出引 脚和1.1M比特的嵌入式寄存器。Cyclone II器件的制造基于300毫米晶圆，采用台积电 90nm、低K值电介质工艺，这种工艺技术是使用低绝缘体过程以确保了快速有效性和低成 本。通过使硅片面积最小化，Cyclone II器件可以在单芯片上支持复杂的数字系统，而在 成本上则可以和ASIC竞争。不像其他用电力功耗和性能来换取低成本的FPGA卖主,Altera 最新一代低价位的FPGAcyclone II FPGA系列，和同类90nmFPGA器件相比，它提高 了百分之六十的性能和降低了一半的功耗。低成本和优化特征使Cyclone II FPGA系列为 各种各样的汽车、消费、通讯、视频处理、测试与测量、和其他最终市场提供理想的解决 方案。在参考设计、系统图，和IP,使用cyclone II FPGA系列可以帮助 你迅速实现最总市场方案开发。低成本的嵌入式解决方案Cyclone II 器件支持 Nios II 嵌入式处理器，能够自己完成自定义的嵌入式处理器。 Cyclone II器件还能够 扩展各种外部存储器和I/O 口或者嵌入式处理器的性能。单个或 多个NiosII嵌入式系统中嵌入式处理器也可以设计成cyclone II设备以提供一些额外的同 时处理的能力或者甚至取代已经在你的系统中存在的嵌入式处理器。使用cyclone II和 nios II 能够拥有成本低和高性能处理方案的共同特点，和普通的产品相比，这个特点能够 延长你的产品的生命周期,提高产品进入市场的时间。低成本 DSP 方案单独使用cycloneII FPGA系列或者或者作为数字信号处理（DSP）协处理器以提高数字 信号处理（DSP）应用的性价比。，你用以下cyclone II的特点和设计支持可以实现高性能 低成本DSP系统： 150个18 x 18乘法器 1.1 M 比特的片内嵌入式存储器 高速的外部寄存器接口 数据处理的知识产权核 Mathworks Simulink 和 Matlab 设计软件与 DSP Builder 的接口 DSP 软件开发程序工具 , Cyclone II 版本Cyclone II 器件包括一个强大的 FPGA 特征建立最优的低成本的应用包括广泛的密度, 记忆，嵌入式乘数，和包装的选择。Cyclone II器件支持低成本运用中常见的各种外部寄存 器界面和 I/O 口协议。 来自 Altera 和合作伙伴 IP 核 使得 CycloneII 界面和协议变的 快速和简单。Cyclone II 设备系列拥有以下的特点: 4,608 到 68,416 LEs 的高密度的结构 M4K 的嵌入式寄存器块 不减少逻辑的情况下有 1.1M 的可用的存储器 每个模块有 4096 比特寄存器 （4,608 比特每个模块包括 512 相同的比特）可变的配置端口有 xl, x2, x4, x& x9, xl6, xl8, x32 和 x36 xl, x2, x4, x& x9, x16,和x18配置的真实的双端口（一个读和一个写，两个读, 或者两个写） 操作 写入操作过程是字节写入 260-MHz 下运行 嵌入式乘法器多达150名的18 -X18-bit乘数器，并且每个乘法器可配置为两个独立的9 X9-bit的250-MHz性能的乘数器可选的输入和输出的寄存器 先进的 I/O 口支持支持高速微分 I / O 标准， 包括 LVDS，mini-LVDS，LVPECL， 相对、微分 HSTL， 和差 分 SSTL支持单端接地I / O标准，包括2.5-V和1.8-V,SSTL级别一和级别二、1.8-V和 1.5-VHSTL 级别一和级别二、 3.3-VPCI 和 pci-x 的 1.0，330 -，2.5-，1.8-， 和 1.5-V LVCMOS， 和 3.3、 2.5 ，1.8-V LVTTL互连外围设备专业组 （PCISIG） PCI 局部总线规格 , 版本 3.0 符合 3.3-V 的 66 或者 32 兆赫的 33 -或 64 位接口的操作 拥有外部 TI PHY 总线接口和 Altera 公司 PCI Express 总线接口 Megacore 功能 的 PCI Express 总线接口。 1 33-MHz pci - x 1.0 的规格兼容性高速外部存储器的支持,包括 Altera IP MegaCore 功能支持的外部单倍数据速率 （SDR）、双倍数据速率（DDR）、DDR2 SDRAM器件以及第二代四倍数据速率 （ QDRII） SRAM器件，这些寄存器主要是为了易于使用。每个I/O组成部分（IOE）有三个专用的存储器：一个输入寄存器，一个输出寄 存器，和一个输入输出寄存器。 可编程总线支持的特点 可编程输出设备扩展的特点 对 I/O 组成部分和逻辑门阵列进行可编程延时 I/O 存储分成单一的 VCCIO 和/或者 VREF 存储设置 I/O 电压标准支持 1.5-, 1.8-, 2.5-, 和 3.3-接口 热插拔操作支持实现了上电之前和上电过程中对器件和三态I/O缓冲的保护 可编程的高端输出 各种样品的终端匹配 灵活的时钟管理电路层次时钟网路高达402.5-MHz的性能每个器件多达四个可编程锁相环（PLL）和提供时钟乘法器和除法器，相移， 可编程占空比, 和外部时钟输出, 被允许的系统时钟管理和频率合成 贯穿整个设备有多大 16个全局时钟线在整个全局时钟网络中 设备的配置快速系列配置的时间限制在100ms以内 减压的特性实现了更小的程序文件存储和更快的配置时间 支持多种配置模式: 主动配置方式，被动配置方式，和 JTAG 配置方式 支持低成本的配置设备的配置设备配置支持多种电压 （包括 3.3, 2.5,或者 1.8 V）知识产权 支持 Altera 宏功能 和 Altera MegaCore 功能，并且支持 Altera 合作伙伴计划 (AMPPSM) 宏功能, 具有广泛的可编程处理器，开芯片和关芯片的接口，强大 的功能,DSP功能和通讯功能和协议。访问的Altera IPMegaStore 可以下载 IP MegaCore 功能 Nios II可编程处理器的支持Cyclone II的一些快速接通型号具有较短的上电复位(POR)时间。拥有快速接通特性的 器件在订购码中用字母“ A 标出。例如： EP2C5A, EP2C8A, EP2C15A, 和 EP2C20A。EP2C5A只能提供汽车速度级型。EP2C8A和EP2C20A只能提供工业级型。EP2C15A只 能提供快速接通型,并且可以提供商业型的和工业型的。标注有 A 的 cyclone II 器件和没有标注 A 的器件具有相同的特性和功能,唯一的不同就是它具有较短的上电复位时间。表格 11 列出了 cyclone II 系列器件的特性。表格12列出了 cyclone II器件的封装和用户I/O管脚数。Cyclone II FPGA 器件特性器件EP2C5EP2C8EP2C15EP2C20EP2C35EP2C50EP2C70逻辑单元4,608& 25614,44818,75233,21650,52868,416M4K RAM块(4 k比特 + 512 校 验比特)26365252105129250总比特数119,808165,888239,616239,616483,840594,4321,152,000嵌入式18x18 乘法器131826263586150PLLs2244444最多用户I/O管脚158182315315475450622表1 注释：1. EP2C15A 只能提供快速接通型。这个器件具有较短的上电复位 (POR) 时间，并且 可以提供商业型的和工业型的。2、EP2C5,EP2C8的,EP2C20选择性地支持快速接通的特点，拥有这个特点的型号用A 在订购码中用标注出来。EP2C5A只能提供汽车速度级型。EP2C8A和EP2C20A只能 提供工业级型。3.这是18x18个乘法器总的所有乘法器。每个器件的9x9乘法器的所有数量乘以2等 于18x18乘法器的数量。Cyclone II器件圭寸装和最多用户I/O管脚器件144-PinTQFP208-PinPQFP240-PinPQFP256-PinFineLineBGA484-PinFineLineBGA484-Pin Ultra FineLine BGA672-PinFineLineBGA896-PinFineLineBGAEP2C589142158EP2C885138182EP2C8A182EP2C15A152315EP2C20142152315EP2C20A152315EP2C35322322475EP2C50294294450EP2C70422622表 1-2 注释：1) 在相同的封装下 cyclone II 设备支持直接替换(例如：你能够在用 484-pin FineLine BGA封装的EP2C20器件和具有相同的封装的EP2C35和EP2C50器件之间替换。(2) Quartus II软件I/O管脚数包括额外的管脚，TDI, TDO, TMS,和TCK，这些管脚 被用为通用的I/O管脚。(3) TQFP = 薄四方扁平封装(4) PQFP = 塑封四方扁平封装(5) EP2C5F256 和 EP2C8F256 器件支持直接替换。不过，不是所有的单一数据选通 (DQS)管脚和相关数据(DQ)管脚都是支持的。用F256封装的EP2C5和EP2C15 器件就不支持直接替换。(6) EP2C5, EP2C8, 和 EP2C15A 器件的 I/O 管脚数包括8个专用时钟管脚，并且这8 个管脚能够被用作数据输入引脚EP2C20, EP2C35, EP2C50,和EP2C70器件的 I/O管脚数包括16个专用时钟管脚，并且这16个管脚能够被用作数据输入引脚。(7) EP2C8A, EP2C15A, 和 EP2C20A 有快速接通的特性，有较短的上电复位的时间。 EP2C15A 只能提供快速接通的型号。(8) EP2C5 选择性地支持快速接通的特点，拥有这个特点的型号用 A 在订购码中用标注出来。EP2C5A只能提供汽车级型号。参考cyclone II的汽车级器件手册部分。在相同的圭寸装下cyclone II设备支持直接替换(例如：你能够在用672-pin FineLine BGA 封装的EP2C35, EPC50和EP2C70器件之间移动cyclone II系列支持的直接替换的例子 在表格1-3中标注出来了。直接替换的意思是你能够替换到某种器件上，这种器件的专门引脚，配置引脚和电源 引脚在高密度器件中有着相同的封装。Taitle 1-3. Total Number ol Non-Miffratable I/O Pins forCydone I! Verficai Miffration PathsVerticalMigration Path144-Pin TQFP20fl-PinPOFF254Pin HnsLine BGA(V464-PinFineLine 9GA(2)m-PinUHra FineLine BGA672-PinFineLine BGA(3)EP2C5 toEP2CB441河EP2C8toEP2C1530EP2C151OEP2C2000EP2C201OEP2C35-16EP2C351OEP2C50-282828EP2C501OEP2C70-2S23表格 1-3 的注释：(1) EP2C5F256 到 EP2C15AF256 和 EP2C5F256 到 EP2C20F256 器件不支持直接替换。(2) 当封装从EP2C20F484器件替换到EP2C50F484器件时，总共有39个I/O引脚的封装没有移动。(3) 当封装从EP2C35F672器件替换EP2C70F672器件时，总共有56个I/O引脚的封装没有移动(4) 除了没有移动的I/O引脚，有34个DQ信号引脚也没有移动。(5) 引脚 484 FBGA 和 484 UBGA 是一样的。为了确保你的电路板布局能够适应已圭寸装的可移动密度，我们在quartus II软件环境下 进行直接替换(选择Assignments菜单，然后Device，然后点击Migration Devices按钮)。 编译之后，检查I/O, DQ, LVDS和其他引脚的信息清单，这些引脚因为选择的路径而不可 用是。表格1-3列出了 cyclone II器件的封装和当封装从一个器件移动到另外一耳光器件的 时不能移动的I/O引脚的数量。Cyclone II器件可用于多达三个级别：-6, -7,和-8,并且-6是最快的级别。表格1-4 列出了 cyclone II器件的速度级别。Table 1-4. Cyclone li Device Speed GradesDevice144-Fin TOFF208Tin PQFP240-FinPOFP25PinFlneLkieBGAAM-Pi nFlneLkieBGA484-HnUltra FineLineBGA672-Pin FineLine BGA89e PinFineLmeBGAEP2C5 f-6, -7,弋-7,-&-7. -aEP2C8-6,-7, -8-7?-&-6,-7, -8EP2C8A (2)-8EP2C15A-6,-7, -8-6.-7, -aEP2C20-8-6.-7,-8EP2C20A (2)-e-8EP2C35-6, -7. -8EP2C50-6.-7, -&七-7, -8-6,-7, -8EP2C70-6. -7,-6. -7? -&表格 1-4 的注释：(1) EP2C5 选择性的支持快速接通的特性，拥有快速接通的特性的器件在订购码中用字 母“A”标出。EP2C5A只能提供汽车级型号。参考cyclone II的汽车级器件手册部 分以了解更详细的信息。(2) EP2C8A和EP2C20A只提供工业级的型号。外文原文资料信息1 外文原文作者：ALTERA公司2 外文原文所在书名或论文题目： Cyclone2_Device_Family_DATA_Sheet3 外文原文来源：出版社或刊物名称、出版时间或刊号、译文部分所在页码：Cyclone2_Device_Family_DATA_Sheet 3-10 页网页地址： 二、外文原文资料：Cyclone2_Device_Family_DATA_SheetKeywords : cycloneII Device Family；features；introduceFollowing the immensely successful first-generation Cyclone devicefamily, Altera Cyclone II FPGAs extend the low-cost FPGA densityrange to 68,416 logic elements (LEs) and provide up to 622 usable I/Opins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs aremanufactured on 300-mm wafers using TSMCs 90-nm low-k dielectricprocess to ensure rapid availability and low cost. By minimizing siliconarea, Cyclone II devices can support complex digital systems on a singlechip at a cost that rivals that of ASICs. Unlike other FPGA vendors whocompromise power consumption and performance for low-cost, Alteraslatest generation of low-cost FPGAsCyclone II FPGAs, offer 60% higherperformance and half the power consumption of competing 90-nmFPGAs. The low cost and optimized feature set of Cyclone II FPGAs makethem ideal solutions for a wide array of automotive, consumer,communications, video processing, test and measurement, and otherend-market solutions. Reference designs, system diagrams, and IP, foundat , are available to help you rapidly develop complete end-market solutions using Cyclone II FPGAs.Low-Cost Embedded Processing SolutionsCyclone II devices support the Nios II embedded processor which allows you to implement custom-fit embedded processing solutions. Cyclone II devices can also expand the peripheral set, memory, I/O, or performance of embedded processors. Single or multiple Nios II embedded processors can be designed into a Cyclone II device to provide additional co-processing power or even replace existing embedded processors in your system. Using Cyclone II and Nios II together allow for low-cost,high-performance embedded processing solutions, which allow you to extend your products life cycle and improve time to market over standard product solutions.Low-Cost DSP SolutionsUse Cyclone II FPGAs alone or as DSP co-processors to improveprice-to-performance ratios for digital signal processing (DSP)applications. You can implement high-performance yet low-cost DSPsystems with the following Cyclone II features and design support: Up to 150 18 x 18 multipliers Up to 1.1 Mbit of on-chip embedded memory High-speed interfaces to external memory DSP intellectual property (IP) cores DSP Builder interface to The Mathworks Simulink and Matlabdesign environment DSP Development Kit, Cyclone II EditionCyclone II devices include a powerful FPGA feature set optimized forlow-cost applications including a wide range of density, memory,embedded multiplier, and packaging options. Cyclone II devices supporta wide range of common external memory interfaces and I/O protocols required in low-cost applications. Parameterizable IP cores from Altera and partners make using Cyclone II interfaces and protocols fast and easy.The Cyclone II device family offers the following features: High-density architecture with 4,608 to 68,416 LEs M4K embedded memory blocks Up to 1.1 Mbits of RAM available without reducing available logic 4,096 memory bits per block (4,608 bits per block including 512 parity bits) Variable port configurations of x1, x2, x4, x8, x9, x16, x18, x32,and x36 True dual-port (one read and one write, two reads, or twowrites) operation for x1, x2, x4, x8, x9, x16, and x18 modes Byte enables for data input masking during writes Up to 260-MHz operation Embedded multipliers Up to 150 18- x 18-bit multipliers are each configurable as two independent 9- x 9-bit multipliers with up to 250-MHz performance Optional input and output registers Advanced I/O support High-speed differential I/O standard support, including LVDS,RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL Single-ended I/O standard support, including 2.5-V and 1.8-V, SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-, and 1.8-V LVTTL Peripheral Component Interconnect Special Interest Group (PCISIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V operation at 33 or 66 MHz for 32- or 64-bit interfaces PCI Express with an external TI PHY and an Altera PCI Express xl Megacore function Altera Corporation 13 February 2008 Cyclone II Device l33-MHz PCI-X l.0 specification compatibility High-speed external memory support, including DDR, DDR2, and SDR SDRAM, and QDRII SRAM supported by drop in Altera IP MegaCore functions for ease of use Three dedicated registers per I/O element (IOE): one input register, one output register, and one output-enable register Programmable bus-hold feature Programmable output drive strength feature Programmable delays from the pin to the IOE or logic array I/O bank grouping for unique VCCIO and/or VREF bank settings MultiVolt I/O standard support for 1.5-, 1.8-, 2.5-, and 3.3-interfaces Hot-socketing operation support Tri-state with weak pull-up on I/O pins before and during configuration Programmable open-drain outputs Series on-chip termination support Flexible clock management circuitry Hierarchical clock network for up to 402.5-MHz performance Up to four PLLs per device provide clock multiplication and division, phase shifting, programmable duty cycle, and external clock outputs, allowing system-level clock management and skew control Up to 16 global clock lines in the global clock network that drive throughout the entire device Device configuration Fast serial configuration allows configuration times less than 100 ms Decompression feature allows for smaller programming file storage and faster configuration times Supports multiple configuration modes: active serial, passive serial, and JTAG-based configuration Supports configuration through low-cost serial configuration devices Device configuration supports multiple voltages (either 3.3, 2.5, or 1.8 V) Intellectual property Altera megafunction and Altera MegaCore function support,and Altera Megafunctions Partners Program (AMPPSM) megafunction support, for a wide range of embedded processors, on-chip and off-chip interfaces, peripheral functions, DSP functions, and communications functions and 1-4 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2008Features protocols. Visit the Altera IPMegaStore at todownload IP MegaCore functions. Nios II Embedded Processor supportThe Cyclone II family offers devices with the Fast-On feature, which offers a faster power-on-reset time. Devices that support the Fast- On feature are designated with an A in the device ordering code. For example, EP2C5A, EP2C8A, EP2C15A, and EP2C20A. The EP2C5A is only available in the automotive speed grade. The EP2C8A and EP2C20A are only available in the industrial speed grade. The EP2C15A is only available with the Fast-On feature and is available in both commercial and industrial grades. The Cyclone II A devices are identical in featureset and functionality to the non-A devices except for support of the faster POR time.Table 1-1 lists the Cyclone II device family features. Table 1-2 lists the Cyclone II device package offerings and maximum user I/O pins.Table 1-1. Cyclone ii FPGA Family Features Pari f of 2FeatureEP2C5 (2)EP2CA (2)EP2C1E (1)mC2Q(2)EP2C36EP2C50EP2C70LEs4,6008.25&14,4481875233.21&S0.E2B6B.416M4K RAM blocks (4Kbits plusS12 parity bits263G5252105129250Total RAM bits1 i9,aoa165.686239.616239,616483,840594.4321JE2.00Embedded multipliers (3)131826263586150PLLs224二-44Table 1-1. Cyclone li FPGA FamHy Features (Part 2 of 2FeatureEP2C5 (2)EP2CA (2)EP2C1& EP2C2O (2)EP2C35EP2C50EP2C70Maximum user I/O pins15818231S31S47B4S0622Notes to Table 11:(1) The EP2C15A is only available with the Fast On feature, which offers a faster POR time. This device is available in both commercial and industrial grade.(2) The EP2C5, EP2C8, and EP2C20 optionally support the Fast On feature, which is designated with an A in the device ordering code. The EP2C5A is only available in the automotive speed grade. The EP2C8A and EP2C20A devices are only available in industrial grade.(3) This is the total number of 18 x 18 multipliers. For the total number of 9 x 9 multipliers perdevice, multiply the total number of 18 x 18 multipliers by 2.Table 1-2. Cyclone ii Package Options & Maximum Useri/0 PinsNoiss (1) (2)Device144PinTOFP (3)2D8-Pin PDFP 河240 PinPQFP256-Fin Fineline BGA4G4-Pin FineLine BGA4B4-Piri Ullra FlneLine BGA672-Pin FineLlneBGA696 Pin FineLlne BGAEP2C5 f6)同89142EP2CBK138182EP2C8A (6), (7182EP2UI5A 儆(7152315EP2C20 (6)14215231 &EP2C2DA 做(7)152315EP2C35 卩32232247SEP2C50 佝294294450EP2C70 (6)一422622Notes to Table 1-2:(1) Cyclone II devices support vertical migration within the same package (for example, you can migrate between the EP2C20 device in the 484-pin FineLine BGA package and the EP2C35 and EP2C50 devices in the same package).(2) The Quartus II software I/O pin counts include four additional pins, TDI, TDO, TMS, and TCK, which are not available as general purpose I/O pins.(3) TQFP: thin quad flat pack.(4) PQFP: plastic quad flat pack.(5) Vertical migration is supported between the EP2C5F256 and the EP2C8F256 devices. However, not all of the DQ and DQS groups are supported. Vertical migration between the EP2C5 and the EP2C15 in the F256 package is not supported.(6) The I/O pin counts for the EP2C5, EP2C8, and EP2C15A devices include 8 dedicated clock pins that can be used for data inputs. The I/O counts for the EP2C20, EP2C35, EP2C50, and EP2C70 devices include 16 dedicated clock pins that can be used for data inputs.(7) EP2C8A, EP2C15A, and EP2C20A have a Fast On feature that has a faster POR time. The EP2C15A is only available with the Fast On option.(8) The EP2C5 optionally support the Fast On feature, which is designated with an A in the device ordering code.The EP2C5A is only available in the automotive speed grade. Refer to the Cyclone II section in the Automotive-Grade Device Handbook.Cyclone II devices support vertical migration within the same package(for example, you can migrate between the EP2C35, EPC50, and EP2C70 devices in the 672-pin FineLine BGA package). The exception to vertical migration support within the Cyclone II family is noted in Table 13.Vertical migration means that you can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities.Table 1-3. Total Number ot Non-Migratabie i/0 Pins for Cyclone li Vertical Miffration PaiftsVerticalMigration Path144-Pin TOFP203-Pin POFP254PinHneLine EGA(1)484-PmHneLine BGA(2)4S4-PmUI1ra FinalliH BGA672-Pin Fine Line BGA(3)EP2C5 toEP2C8441河EP2C8to EP2C15就iEP2C151OEP2C2000EP2C201OEP2C3516EP2C351EP2C50-28282BEP2C501OEP2C70282BNotes to Table 13:(1) Vertical migration between the EP2C5F256 to the EP2C15AF256 and the EP2C5F256 to the EP2C20F256 devices is not supported.(2) When migrating from the EP2C20F484 device to the EP2C50F484 device, a total of 39 I/O pins are non-migratable.(3) When migrating from the EP2C35F672 device to the EP2C70F672 device, a total of 56 I/O pins are non-migratable.(4) In addition to the one non-migratable I/O pin, there are 34 DQ pins that are non-migratable.(5) The pinouts of 484 FBGA and 484 UBGA are the same.To ensure that your board layout supports migratable densities within one package offering, enable the applicable vertical migration path within the Quartus II software (go to Assignments menu, then Device, then click the Migration Devices button). After compilation, check the information messages for a full list of I/O, DQ, LVDS, and other pins that are not available because of the selected migration path. Table 1-3 lists the Cyclone II device package offerings and shows the total number ofnon-migratable I/O pins when migrating from one density device to a larger density device.Cyclone II devices are available in up to three speed grades: -6, -7, and -8, with -6 being the fastest. Table 1-4 shows the Cyclone II device speed-grade offerings.Table 1-4. Cyclone ii Device Speed GradesDevice144-PinTOFF208Tin POFP240 Pin POFP254円 n FineLlneBGA4E4-Pin FineLine BGA484-PinUllra FineLineBGA672-Pin FineLlne