Agilent3070测试程序开发流程.ppt

Agilent3070测试程序开发流程,3070测试程序开发流程概述,1：CAD file 转换,2: Board 文件的电路板信息输入以及测试测试信息的定义,3：IPG Test Consultant自动生成测试程序的文件,4：制作夹具,5：用经过确认的好板调试程序,6：发布到生产线并长期维护,7：ECO变跟,Process,Files,Tools,ECO,board,testability.rpt,Fixture Files,Individual Test Files,config,testplan,Translate CAD,1,Generate Test & Fixture files,3,Build & Verify test Fixture,4,Turn-On / Debug all Tests,5,Release to Production & Long Term Support,6,Describe board & system,2,Custom libraries,board_xy,Collect the files needed,0,Test Development Flowchart,Setp.0 Files Needed for Development,BOM,Schematic,Library BSDL,Config,Test Strategy,原始资料和物品,程序发展前所需资料和物品：1：CAD file and BOM 2: Schematics(电路图） 3：config file(机台配置文件）4：Golden Board 5：Custom library(准备library) 6：BSDL file (for boundary scan) 7: TDF file (for XOR tree ) 8:Test Strategy规划,CAD,datasheet,Step.1 Translate CAD,Translate CAD into Agilent 3070 Board Format,Fixture house free service Agilent CAD format translator Translate BOM into board file,CAD file,Translation tool,board,board_xy,夹具厂商会用专门的转换软件将CAD file Translation 3070 board format, 即board file和board_ xy file,Step 2 : Define Test Strategy,Digital device Digital Library TestJet Boundary Scan NAND tree Power Supply Fixture Size & Type,规划测试方案：1：制定出针对IC,BGA,LED,晶振,connector等器件的测试策略,如:digital测试，testjet测试，boundary Scan测试，NAND tree 和XOR tree测试等 2：power sequence 3：Fixture 的大小和类型等的规划！,Step.3 Describe Board & System,1：首先将CAD file转出的board file和board_xy file做语法check,看有无语法错误，会用到的指令为：check board “board”和check boardxy “ board_xy”,Check board “board”,Check boardxy “board_xy”,Step.3 Describe Board & System,2:在check board和board_xy file后，如果没有error和warning后，就可以用将board和 board_xy载入到board consultant中,Board consultant,Step.3 Describe Board & System,View/Edit Physical Board Data Edit Board Outline Enter Board Tooling Holes,Edit Board Outline让我们可以修改板子的外框形状,Enter Board Tooling Holes让我们可以随自己的需要选择合适的Tooling Houles,Step.3 Describe Board & System,View/Edit Board Description Enter Capacitor Enter Resistor Enter Inductor Enter FET Enter Pin Library Enter Transistor Enter Internal Devices ,可以对每个元器件做编辑和定义测试类型和上下限的设定和fail时希望show出的错误信息等，特别是定义IC的测试信息时，要注意：1: part number一定要和library实际文件名保持一致，2：testjet 设定为auto,Step.3 Describe Board & System,View/Edit Test System Data Enter Power Node Data Enter Fixed Node Data Enter Board-Level Disables/Conditions Enter IPG Global Options Enter Family Options Enter Fixture Options Enter GP-Relay Connections Enter Board Keepout Areas Enter Groups Enter Extra Probing Locations,Power node定义我们上电的点,Fixed node定义我们待测板上电源点和逻辑状态不能改变的点,IPG测试选项设定,Family options逻辑电平设定,Fixture 设定,Step.3 Describe Board & System,Compile & Verify Compile “config” file Verify fixture type Verify configuration size Show device using Agilent Testjet Verify Bottom Keepouts for Agilent Testjet Verify Node Probing Access Verify Power Node Probing Access Verify Ground Node Probing Access ,对前面的设定进行verify的动作和最后的确认,Compile config对机台配置文件进行编译,根据提示依次确认测试信息的准确性,Step.3 Describe Board & System,View/Edit Library Data Enter Library Paths Display Device Library Instructions Display Part Library Instructions Display Safeguard File Instructions,编辑library,对没有library的Device需要手写，会用到的Tool有：Setup Editor和Part Description Editor,这两个工具是我们写library会经常用到的,一般我们会在程序当前目录下新建一custom_lib,将写好的 library放在此目录下面，而且还应创建一个非常重要的safeguard文件，其中包含所有IC的part number,safeguard文件的作用是对被测IC以外的IC进行保护，防止ICT在on power 测试过程中将IC烧坏，最大限度保护IC,注意：在编写Library时应尽可能的包含Disable信息,Step.3 Describe Board & System,Compile & Verify Save Board Files Compile Modified Libraries Compile Modified Safeguard Files Verify Missing Libraries Verify Disable Methods Exisit Verify Boundary-scan chains ,这个部分主要是对Device的library进行编译和确认，有无library缺失情况，还有关于Boundary Scan library的写法等,Step.3 Describe Board & System,最后Verify和编译，这一步骤是对我们前面所做动作的一个检验，它是将板子设定和Library设定综合对照来进行verify和编译,Final Compile & Verify Save Board Files Compile “board” File Compile “board_xy” File Show IPG device summary Verify IPG Device Disable Results Verify Safeguard Inhibit Result,这两者必须完全匹配才能编译成功，board 编译成功可以说程序发展已经完成一半了，compile board是3070发展程序非常重要也是最困难的一个步骤,Step.3 Describe Board & System,Testability Report Number of Devices - Analog - Digital Number of ICs - Library test, ( library missing ? ) - Testjet test, Connect Check Node Information - inaccessible nodes - critical nodes More Reviews,最后run Testability report, 可测试报告，他会告诉我们如果按照这样的设定run出来的程序质量高不高，还有没有可以改善的地方等！,