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CS 152 Computer Architecture and Engineering Lecture 1-Introduction What is Computer Architecture?2ApplicationPhysicsGap too large to bridge in one stepIn its broadest definition,computer architecture is the design of the abstraction layers that allow us to implement information processing applications efficiently using available manufacturing technologies.(but there are exceptions,e.g.magnetic compass)3Abstraction Layers in Modern SystemsAlgorithmGates/Register-Transfer Level(RTL)ApplicationInstruction Set Architecture(ISA)Operating System/Virtual MachinesMicroarchitectureDevicesProgramming LanguageCircuitsPhysicsEE141CS150CS162CS170CS164EE143CS152UCB EECS CoursesCompatibilityCost of software development makes compatibility a major force in marketArchitecture continually changing4ApplicationsTechnologyApplications suggest how to improve technology,provide revenue to fund developmentImproved technologies make new applications possible5Computing Devices ThenEDSAC,University of Cambridge,UK,19496Computing Devices NowRobotsSupercomputersAutomobilesLaptopsSet-top boxesSmart phonesServersMedia PlayersSensor NetsRoutersCamerasGames71101001000100001978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006Performance(vs.VAX-11/780)25%/year52%/year?%/yearUniprocessor Performance VAX :25%/year 1978 to 1986 RISC+x86:52%/year 1986 to 2002 RISC+x86:?%/year 2002 to presentFrom Hennessy and Patterson,Computer Architecture:A Quantitative Approach,4th edition,October,2006What happened?8from KurzweilMajor Technology GenerationsBipolarnMOSCMOSpMOSRelaysVacuum TubesElectromechanical?9The End of the Uniprocessor EraSingle biggest change in the history of computing systems10This Years CS252CS152 focuses on interaction of software and hardwaremore architecture and less digital engineeringmore useful for OS developers,compiler writers,performance programmersMuch of the material youll learn this term was previously in CS252Some of the current CS61C,I first saw in CS252 over 20 years ago!Maybe every 10 years,shift CS252-CS152-CS61C?Class contains labs based on various different machine designsExperiment with how architectural mechanisms work in practice on real software.Designs written in Chisel hardware description languageGet to see(and modify)all the working parts of a modern microprocessorHopefully FPGA versions later in course!11Related CoursesCS61CCS 152CS 150Basic computer organization,first look at pipelines+cachesComputer Architecture,First look at parallel architecturesDigital Logic Design,FPGAsStrongPrerequisiteCS 250VLSI Systems DesignCS 252Graduate Computer Architecture,Advanced Topics12CS152 Executive SummaryThe processor you built in CS61CPlus,the technology behind chip-scale multiprocessors(CMPs)and graphics processing units(GPUs)What youll understand and experiment with in CS15213CS152 AdministriviaInstructor:Prof.Krste Asanovic,krsteeecsOffice:579 Soda Hall(inside Par Lab)Office Hours:Mon.5:00-6:00PM(email to confirm),579 SodaT.A.:Yunsup Lee,yunsupeecsOffice Hours:Tuesdays 1-2PM,751 SodaLectures:Tu/Th,2-3:30PM,310 Soda(Possible room change!)Section:F 10:30AM-12M,9 EvansText:Computer Architecture:A Quantitative Approach,Hennessey and Patterson,5th Edition(2012)Readings assigned from this edition,some readings available in older editions see web page.Web page:http:/inst.eecs.berkeley.edu/cs152Lectures available online by noon before classPiazzza:http:/ Structure and SyllabusFive modules1.Simple machine design(ISAs,microprogramming,unpipelined machines,Iron Law,simple pipelines)2.Memory hierarchy(DRAM,caches,optimizations)plus virtual memory systems,exceptions,interrupts3.Complex pipelining(score-boarding,out-of-order issue)4.Explicitly parallel processors(vector machines,VLIW machines,multithreaded machines)5.Multiprocessor architectures(memory models,cache coherence,synchronization)15CS152 Course Components15%Problem Sets(one per module)Intended to help you learn the material.Feel free to discuss with other students and instructors,but must turn in your own solutions.Grading based mostly on effort,but quizzes assume that you have worked through all problems.Solutions released after PSs handed in.35%Labs(one per module)Labs use advanced full system simulators(new Chisel simulators this year,no Simics)Directed plus open-ended sections to each lab50%Quizzes(one per module)In-class,closed-book,no calculators,no smartphones,no laptops,.Based on lectures,readings,problem sets,and labs 16CS152 LabsEach lab has directed plus open-ended assignmentsDirected portion(2/7)is intended to ensure students learn main concepts behind labEach student must perform own lab and hand in their own lab reportOpen-ended assignment(5/7)is to allow you to show your creativityRoughly a one-day“mini-project”E.g.,try an architectural idea and measure potential,negative results OK(if explainable!)Students can work individually or in groups of two or threeGroup open-ended lab reports must be handed in separatelyStudents can work in different groups for different assignmentsLab reports must be readable English summaries not dumps of log files!RISC-V ISARISC-V is a new simple,clean,extensible ISA we developed at Berkeley for education and researchRISC-I/II,first Berkeley RISC implementationsBerkeley research machines SOAR/SPUR considered RISC-III/IV Both of the dominant ISAs(x86 and ARM)are too complex to use for teachingRISC-V ISA manual available on web pageFull GCC-based tool chain available17Chisel simulatorsChisel is a new hardware description language we developed at Berkeley based on ScalaConstructing Hardware in a Scala Embedded LanguageLabs will use RISC-V processor simulators derived from Chisel processor designsGives you much more detailed information than other simulatorsCan map to FPGA or real chip layoutYou need to learn some minimal Chisel in CS152,but well make Chisel RTL source available so you can see all the details of our processorsCan do lab projects based on modifying the Chisel RTL code if desired18Chisel Design Flow19Chisel Design DescriptionC+codeFPGA VerilogASIC VerilogC+SimulatorC+CompilerChisel CompilerFPGA EmulationFPGA ToolsGDS LayoutASIC Tools20Computer Architecture:A Little HistoryThroughout the course well use a historical narrative to help understand why certain ideas aroseWhy worry about old ideas?Helps to illustrate the design process,and explains why certain decisions were takenBecause future technologies might be as constrained as older onesThose who ignore history are doomed to repeat itEvery mistake made in mainframe design was also made in minicomputers,then microcomputers,where next?21Charles Babbage 1791-1871Lucasian Professor of Mathematics,Cambridge University,1827-183922Charles BabbageDifference Engine 1823Analytic Engine 1833The forerunner of modern digital computer!Application Mathematical Tables Astronomy Nautical Tables NavyBackground Any continuous function can be approximated by a polynomial-Weierstrass Technology mechanical-gears,Jacquards loom,simple calculators23Difference EngineA machine to compute mathematical tablesWeierstrass:Any continuous function can be approximated by a polynomialAny polynomial can be computed from difference tablesAn examplef(n)=n2+n+41d1(n)=f(n)-f(n-1)=2nd2(n)=d1(n)-d1(n-1)=2f(n)=f(n-1)+d1(n)=f(n-1)+(d1(n-1)+2)all you need is an adder!nd2(n)d1(n)f(n)041122232424684347536124Difference Engine1823Babbages paper is published1834The paper is read by Scheutz&his son in Sweden1842 Babbage gives up the idea of building it;he is onto Analytic Engine!1855Scheutz displays his machine at the Paris World FareCan compute any 6th degree polynomialSpeed:33 to 44 32-digit numbers per minute!Now the machine is at the Smithsonian25Analytic Engine1833:Babbages paper was publishedconceived during a hiatus in the development of the difference engineInspiration:Jacquard Loomslooms were controlled by punched cardsThe set of cards with fixed punched holes dictated the pattern of weave programThe same set of cards could be used with different colored threads numbers1871:Babbage diesThe machine remains unrealized.It is not clear if the analytic engine could be built using the mechanical technology of the time26Analytic EngineThe first conception of a general-purpose computer1.The store in which all variables to be operated upon,as well as all those quantities which have arisen from the results of the operations are placed.2.The mill into which the quantities about to be operated upon are always brought.The program Operation variable1 variable2 variable3An operation in the mill required feeding two punched cards and producing a new punched card for the store.An operation to alter the sequence was also provided!27The first programmer Ada Byron aka “Lady Lovelace”1815-52Adas tutor was Babbage himself!28Babbages InfluenceBabbages ideas had great influence later primarily because ofLuigi Menabrea,who published notes of Babbages lectures in ItalyLady Lovelace,who translated Menabreas notes in English and thoroughly expanded them.“.Analytic Engine weaves algebraic patterns.”In the early twentieth century-the focus shifted to analog computers butHarvard Mark I built in 1944 is very close in spirit to the Analytic Engine.29Harvard Mark IBuilt in 1944 in IBM Endicott laboratoriesHoward Aiken Professor of Physics at HarvardEssentially mechanical but had some electro-magnetically controlled relays and gearsWeighed 5 tons and had 750,000 componentsA synchronizing clock that beat every 0.015 seconds(66Hz)Performance:0.3 seconds for addition 6 seconds for multiplication 1 minute for a sine calculationDecimal arithmeticNo Conditional Branch!Broke down once a week!30Linear Equation SolverJohn Atanasoff,Iowa State University1930s:Atanasoff built the Linear Equation Solver.It had 300 tubes!Special-purpose binary digital calculatorDynamic RAM(stored values on refreshed capacitors)Application:Linear and Integral differential equationsBackground:Vannevar Bushs Differential Analyzer-an analog computerTechnology:Tubes and Electromechanical relaysAtanasoff decided that the correct mode of computation was using electronic binary digits.31Electronic Numerical Integratorand Computer(ENIAC)Inspired by Atanasoff and Berry,Eckert and Mauchly designed and built ENIAC(1943-45)at the University of PennsylvaniaThe first,completely electronic,operational,general-purpose analytical calculator!30 tons,72 square meters,200KWPerformanceRead in 120 cards per minuteAddition took 200 ms,Division 6 ms1000 times faster than Mark INot very reliable!Application:Ballistic calculationsangle=f(location,tail wind,cross wind,air density,temperature,weight of shell,propellant charge,.)WW-2 Effort32Electronic Discrete Variable Automatic Computer(EDVAC)ENIACs programming system was externalSequences of instructions were executed independently of the results of the calculationHuman intervention required to take instructions“out of order”Eckert,Mauchly,John von Neumann and others designed EDVAC(1944)to solve this problemSolution was the stored program computer“program can be manipulated as data”First Draft of a report on EDVAC was published in 1945,but just had von Neumanns signature!In 1973 the court of Minneapolis attributed the honor of inventing the computer to John Atanasoff33Stored Program Computermanual controlcalculatorsautomatic controlexternal(paper tape)Harvard Mark I,1944Zuses Z1,WW2internal plug boardENIAC 1946read-only memoryENIAC 1948read-write memoryEDVAC 1947(concept)The same storage can be used to store program and dataProgram=A sequence of instructionsHow to control instruction sequencing?EDSAC 1950 Maurice Wilkes34Technology IssuesENIACEDVAC18,000 tubes4,000 tubes20 10-digit numbers2000 word storagemercury delay linesENIAC had many asynchronous parallel unitsbut only one was active at a timeBINAC:Two processors that checked each otherfor reliability.Didnt work well because processors never agreed35Dominant Problem:Reliability Mean time between failures (MTBF)MITs Whirlwind with an MTBF of 20 min.was perhaps the most reliable machine!Reasons for unreliability:1.Vacuum Tubes 2.Storage medium acoustic delay lines mercury delay lines Williams tubes SelectionsReliability solved by invention of Core memory by J.Forrester 1954 at MIT for Whirlwind project36Commercial Activity:1948-52IBMs SSEC(follow on from Harvard Mark I)Selective Sequence Electronic Calculator150 word store.Instructions,constraints,and tables of data were read from paper tapes.66 Tape reading stations!Tapes could be glued together to form a loop!Data could be output in one phase of computation and read in the next phase of computation.37And then there was IBM 701IBM 701-30 machines were sold in 1953-54used CRTs as main memory,72 tubes of 32x32b eachIBM 650 -a cheaper,drum based machine,more than 120 were sold in 1954 and there were orders for 750 more!Users stopped building their own machines.Why was IBM late getting into computer technology?IBM was making too much money!Even without computers,IBM revenues were doubling every 4 to 5 years in 40s and 50s.38Computers in mid 50sHardware was expensiveStores were small(1000 words)No resident system software!Memory access time was 10 to 50 times slower than the processor cycle Instruction execution time was totally dominated by the memory reference time.The ability to design complex control circuits to execute an instruction was the central design concern as opposed to the speed of decoding or an ALU operation Programmers view of the machine was inseparable from the actual hardware implementation 39The IBM 650(1953-4)From 650 Manual,IBMMagnetic Drum(1,000 or 2,00010-digit decimal words)20-digit accumulatorActive instruction(including next program counter)Digit-serial ALU40Programmers view of the IBM 650A drum machine with 44 instructionsInstruction:60 1234 1009“Load the contents of location 1234 into the distribution;put it also into the upper accumulator;set lower accumulator to zero;and then go to location 1009 for the next instruction.”Good programmers optimized the placement of instructions on the drum to reduce latency!41The Earliest Instruction SetsSingle Accumulator -A carry-over from the calculators.LOADxAC MxSTORExMx (AC)ADDxAC (AC)+MxSUBxMULxInvolved a quotient registerDIVxSHIFT LEFTAC 2 (AC)SHIFT RIGHTJUMPxPC xJGExif(AC)0 then PC xLOAD ADR xAC Extract address field(Mx)STORE ADRxTypically less than 2 dozen instructions!42Programming:Single Accumulator MachineLOOPLOADNJGEDONEADDONESTORENF1LOADAF2ADDBF3STORECJUMPLOOPDONEHLTCi Ai+Bi,1 i nHow to modify the addresses A,B and C?ABCNONEcode-n143Self-Modifying CodeLOOPLOADNJGEDONEADDONESTORENF1LOADAF2ADDBF3STORECJUMPLOOPDONEHLTmodify theprogramfor the nextiterationEach iteration involves total book-keepinginstructionfetches operand fetches stores Ci Ai+Bi,1 i nLOAD ADRF1ADDONESTORE ADRF1LOAD ADRF2ADDONESTORE ADRF2LOAD ADRF3ADDONESTORE ADRF3JUMPLOOPDONEHLT17105148444Modify existing instructionsLOADx,IXAC Mx+(IX)ADDx,IXAC (AC)+Mx+(IX).Add new instructions to manipulate index registersJZix,IXif(IX)=0 then PC x else IX (IX)+1LOADix,IXIX Mx (truncated to fit IX).Index RegistersTom Kilburn,Manchester University,mid 50sOne or more specialized registers to simplifyaddress calculationIndex registers have accumulator-like characteristics45Using Index RegistersLOADi-n,IXLOOPJZiDONE,IXLOAD LASTA,IXADD LASTB,IXSTORE LASTC,IXJUMP LOOPDONEHALT Program does not modify itself Efficiency has improved dramatically(ops/iter)with index regs without index regs instruction fetch17(14)operand fetch10(8)store 5(4)Costs:Instructions are 1 to 2 bits longerIndex registers with ALU-like circuitry Complex controlALASTACi Ai+Bi,1 i n5(2)2146Operations on Index RegistersTo increment index register by kAC (IX)new instructionAC (AC)+kIX (AC)new instructionalso the AC must be saved and restored.It may be better to increment IX directly INCik,IX IX (IX)+kMore instructions to manipulate index registerSTOREix,IX Mx (IX)(extended to fit a word).IX begins to look like an accumulator several index registersseveral accumulators General Purpose Registers47Evolution of Addressing Modes1.Single accumulator,absolute addressLOADx2.Single accumulator,index registersLOADx,IX3.IndirectionLOAD(x)4.Multiple accumulators,index registers,indirectionLOADR,IX,x orLOADR,IX,(x)the meaning?R MMx+(IX)or R MMx+(IX)5.Indirect through registersLOADRI,(RJ)6.The worksLOADRI,RJ,(RK)RJ=index,RK=base addr48Variety of Instruction FormatsOne address formats:Accumulator machinesAccumulator is always other source and destination operandTwo address formats:the destination is same as one of the operand sources(Reg Reg)to RegRI (RI)+(RJ)(Reg Mem)to RegRI (RI)+Mxx can be specified directly or via a registereffective address calculation for x could include indexing,indirection,.Three address formats:One destination and up to two operand sources per instruction(Reg x Reg)to RegRI (RJ)+(RK)(Reg x Mem)to RegRI (RJ)+Mx49Zero Address FormatsOperands on a stackadd Msp-1 Msp+Msp-1 loadMsp MMspStack can be in registers or in memory(usually top of stack cached in registers)CBASPRegister50Burroughs B5000 Stack Architecture:An ALGOL Machine,Robert Barton,1960Machine implementation can be completely hidden if the programmer is provided only a high-level language interface.Stack machine organization because stacks are convenient for:1.expression evaluation;2.subroutine calls,recursion,nested interrupts;3.accessing variables in block-structured languages.B6700,a later model,had many more innovative featurestagged datavirtual memorymultiple processors and memories51abcEvaluation of Expressions(a+b*c)/(a+d*c-e)/+*+ae-acdc*bReverse Polisha b c*+a d c*+e-/push apush bpush cmultiply*Evaluation Stackb*c52aEvaluation of Expressions(a+b*c)/(a+d*c-e)/+*+ae-acdc*bReverse Polisha b c*+a d c*+e-/add+Evaluation Stackb*ca+b*c53Hardware organization of the stackStack is part of the processor state stack must be bounded and small number of Registers,not the size of main memory Conceptually stack is unboundeda part of the stack is included in the processor state;the rest is kept in the main memory54Stack Operations andImplicit Memory ReferencesSuppose the top 2 elements of the stack are kept in registers and the rest is kept in the memory.Each push operation1 memory reference pop operation 1 memory reference No Good!Better performance by keeping the top N elements in registers,and memory references are made only when register stack overflows or underflows.Issue-when to Load/Unload registers?55Stack Size and Memory Referencesprogramstack(size=2)memory refspush aR0apush bR0 R1bpush cR0 R1 R2c,ss(a)*R0 R1sf(a)+R0push aR0 R1apush dR0 R1 R2d,ss(a+b*c)push cR0 R1 R2 R3c,ss(a)*R0 R1 R2sf(a)+R0 R1sf(a+b*c)push eR0 R1 R2e,ss(a+b*c)-R0 R1sf(a+b*c)R0a b c*+a d c*+e-/4 stores,4 fetches(implicit)56Stack Size and Expression Evaluationprogramstack(size=4)push aR0push bR0 R1push cR0 R1 R2*R0 R1+R0push aR0 R1push dR0 R1 R2push cR0 R1 R2 R3*R0 R1 R2+R0 R1push eR0 R1 R2-R0 R1R0a b c*+a d c*+e-/a and c are“loaded”twicenot the bestuse of registers!57Register Usage in a GPR MachineMore control over register usage since registers can be named explicitlyLoadRi mLoadRi(Rj)LoadRi(Rj)(Rk)-eliminates unnecessary Loads and Stores-fewer Registersbut instructions may be longer!LoadR0aLoadR1cLoadR2bMulR2R1(a+b*c)/(a+d*c-e)Reuse R2AddR2R0LoadR3dMulR3R1AddR3R0Reuse R3LoadR0eSubR3R0DivR2R3Reuse R058Stack Machines:Essential featuresIn addition to push,pop,+etc.,the instruction set must provide the capability torefer to any element in the data areajump to any instruction in the code areamove any element in the stack frame to the topmachinery tocarry out+,-,etc.stackSPDP PCdata.abcpush apush bpush c*+push e/code59Stack versus GPR OrganizationAmdahl,Blaauw and Brooks,19641.The performance advantage of push down stack organization is derived from the presence of fast registers and not the way they are used.2.“Surfacing”of data in stack which are“profitable”is approximately 50%because of constants and common su
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