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SMDK-V210JJSEFS MANUAL_REV 0.0PreliminaryUser s Manual(SMDK S5PV210 Rev0.0)Developme nt Kitfor S5PV210Dec 02, 2009REV 0.0ELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0Importa nt NoticeELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0ELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0The in formati on in this publicati on has bee n carefully checked and is believed to be en tirely accurate at the time of publicati on. Samsu ng assumes no respon sibility, however, for possible errors or omissi ons, or for any con seque nces result ing from the use of the information contained herein.Samsu ng reserves the right to make cha nges in its products or product specificati ons with the intent to improve function or design at any time and without no tice and is not required to update this docume ntati on to reflect such cha nges.This publicati on does not con vey to a purchaser of semic on ductor devices described here in any lice nse un der the pate nt rights of Samsu ng or others.Samsu ng makes no warra nty, represe ntati on, or guara ntee regard ing the suitability of its products for any particular purpose, nor does Samsu ng assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, in clud ing without limitation any consequential or in cide ntal damages.S5PV210 RISC Microprocessor SMDK S5PV210 User s manual, Revision 0.0Copyright ? 2008 Samsung Electronics Co.丄td.Typical parameters can and do vary in differe nt applicati ons. All operati ng parameters, in clud ing Typicals must be validated for each customer applicati on by the customers tech ni cal experts.Samsu ng products are not desig ned, inten ded, or authorized for use as comp onents in systems inten ded for surgical impla nt into the body, for other applicati ons inten ded to support or susta in life, or for any other application in which the failure of the Samsu ng product could create a situati on where pers onal injury or death may occur.Should the Buyer purchase or use a Samsu ng product for any such uninten ded or un authorized applicati on, the Buyer shall indemnify and hold Samsu ng and its officers, employees, subsidiaries, affiliates, and distributors harmless aga inst all claims, costs, damages, expe nses, and reas on able attor ney fees aris ing out of, either directly or in directly, any claim of pers onal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsu ng was n eglige nt regard ing the desig n or man ufacture of said productELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics Co.,Ltd.Samsu ng Electro nics Co., Ltd.San #24 No ngseo-Do ng, Giheu ng-GuYon gi n-City Gyeon ggi-Do, Korea446-711Home Page: E-Mail: mobilesol.csPrinted in the Republic of KoreaELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0ELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0ELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0Revisi on HistoryRev.NoDescription of ChangeRefer toAuthor(s)Effective Date(MM/DD/YY)0.00-Initial Release (SMDK S5PV210 Rev0.00)AP developme ntDec, 02, 2009Table of Contents1 INTRODUCTION61.1 SYSTEM OVERVIEW 61.2 SMDK S5PV210 FEATURES 82 SMDK S5PV210 REAL VIEW92.1 SMDK S5PV210 CPU BOARD REAL VIEW 92.2 SMDK S5PV210 BASE BOARD REAL VIEW112.3 SMDK S5PV210 LCD BOARD REAL VIEW133 CIRCUIT DESCRIPTION 133.1 POWER DISTRIBUTION TREE133.2 FUNCTIONAL BLOCK DIAGRAM164 SMDK S5PV210 SYSTEM CONFIGURATIONS 174.1 PLL CLOCK SOURCE SELECTION204.2 BOOT MODE SELECTION204.2.1 SwitchConfiguration204.3 CONFIGURATION SWITCH DESCRIPTION IN CPU BOARD214.3.1 CFG3:SELECTION FOR CS#4,#5214.3.2 J2: SELECTION for In terrupt of Ext. On eNAND 214.3.3 CFG2:Con figuratio n of MMC slot 0224.3.4 CFG1: TSI I/F224.3.5 J3: PSHOLD selection224.3.6 JP1: JIG ON selection224.4 CONFIGURATION SWITCH DESCRIPTION IN BASE BOARD244.4.1 CFGB1:SROMBANK0CHIPSELECTOR244.4.2 CFGB2:SROMBANK1CHIPSELECTOR244.4.3 CFGB3:SROMBANK2CHIPSELECTOR244.4.4 CFGB4:SROMBANK3CHIPSELECTOR244.4.5 CFGB 5:SROMBANK4CHIPSELECTOR254.4.6 CFGB6:SROMBANK5CHIPSELECTOR254.4.7 CF,MODEM,CAM_B,KEY,MHL,SROM ADDR SWITCHING254.4.8 CFGB10: Audio Port264.4.9 CFGB11: Audio Codec(WM8580) Master clock selection264.4.10 CFGB12: Audio Device In put/Output Connection274.4.11 CFGB13: UART/IrDA Connection274.5 LED & SWITCH Description274.5.1 LED description274.5.2 Switch description285 SMDK Daughter Board 295.1 Exter nal OneNAND295.1.1 Real view295.1.2 Schematic295.2 CSI Daughter Board295.2.1 Real view295.2.2 Schematic305.3 DSI Daughter Board305.3.1 Real view315.3.2 Schematic316 SMDK SCHEMATIC REVISION HISTORY. 327 SMDK SCHEMATIC 32Figure ListFigure 1 S5PV210 Fun cti onal Block Diagram7Figure 2 S5PV210 CPU BOARD TOP VIEW 9Figure 3 S5PV210 CPU BOARD BOTTOM VIEW 10Figure 5 S5PV210 BASE BOARD BOTTOM VIEW 12Figure 6 S5PV210 LCD BOARD TOP VIEW 13Figure 7 S5PV210 BASE BOARD POWER DISTRIBUTION TREE 14Figure 8 S5PV210 CPU BOARD POWER DISTRIBUTION TREE 15Figure 9 S5PV210 SMDK FUNCTIONAL BLOCK DIAGRAM 16Figure 10 Exter nal OneNAND 29Figure 11 CSI Daughter Board 30Figure 12 DSI Daughter Board 31Figure 13 Camera module ?! ?1 INTRODUCTION1.1 SYSTEM OVERVIEWSMDK S5PV210 ( S5PV210 Developme nt Kit) is a platform for code developme nt of SAMSUNGS S5PV210 16/32-bit RISC microco ntroller (ARM-CORTEX A8). S5PV210 is used in han d-held devices and gen eral applicati ons.The S5PV210 is a 32-bit RISC cost-effective, low power, high performa nee microprocessor solution for mobile phones and general applications, and integrates an ARM Cortex-A8 which impleme nts the ARM architecture V7-A with support ing n umerous peripherals.To provide optimized Hardware (H/W) performa nee for the 3G and 3.5G commu ni cati on services, S5PV210 adopts 64-bit in ter nal bus architecture and in cludes many powerful hardware accelerators for tasks such as moti on video process ing, display con trol and scali ng. In tegrated Multi Format Codec (MFC) supports en codi ng and decodi ng of MPEG-1/2/4, H.263, H.264 and decod ing of VC1, Divx. This Hardware accelerators support realtime video conferencing and An alog TV out, HDMI for NTSC and PAL modeThe S5PV210 has an optimized in terface to external memory capable of sustai ning the dema nding memory ban dwidths required in high-e nd commu ni cati on services. The memory system has Flash/ ROM external memory ports for parallel access and DRAM port for high ban dwidth. DRAM port can be con figured to support LPDDR1(=mobile DDR), DDR2 or LPDDR2.Flash/ROM Port supports NAND Flash, NOR-Flash, On eNAND, SRAM and ROM type exter nal memory.To reduce total system cost and enhance overall functionality, S5PV210 includes many hardware peripherals such as TFT 24-bit true color LCD con troller, Camera In terface, MIPI DSI, CSI-2, System Manager for power management, ATA I/F, 4 UART, 24-channel DMA, 4 Timers, General I/O Ports, 3 IIS, S/PDIF, 3 IIC-BUS in terface, 3 HS-SPI, USB Host 2.0, USB OTG 2.0 operati ng at high speed (480Mbps), 4 SD Host & High Speed Multi-Media Card In terface and 4 PLLs for clock gen erati on.Package on Package (POP) option with MCP is available for small form factor applications.ELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0ELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0System PeripheralRTCPLL x 4Timer with PWM (4ch)Watchdog TimerDMA (24ch)Keypad (14x8)TS-ADC (12bit/10ch)fMultimedia12MP Camera IF / MIPI CSI-21080p 30fps MFCCodec -H.263/H.264/MPEG4Decoder -MPEG2/VC-1/Divx128KB64KBRAMROMMulti layer AHB/AXI BusCryptoAudioEnginesDSPPowerMan ageme ntClock gati ng /Power gati ng /Dyn amic VoltageFrequency Scali ng2D VG / 3D Graphics engineNTSC / PAL TV out& HDMIJPEG CodecTFT LCD con trollerXGA resolution丿Memory In terfaceSRAM / ROM(Flex) On eNANDSLC / MLC NAND with 16bit ECCLPDDR1 / On eDRAMLPDDR2/DDR2L,Figure 1 S5PV210 Functional Block DiagramELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.01.2 SMDK S5PV210 FEATURESThe SMDK S5PV210 (S5PV210 Developme nt Kit) highlights the basic system-based hardware design which uses the S5PV210. It can evaluate the basic operations of the S5PV210 and assist in develop ing codes.The features of SMDK S5PV210 in clude:- Microco ntroller : S5PV210 (16/32 bit RISC microco ntroller,ARM-CORTEX A8 )- Exter nal memory.AMD 8Mbit NOR Flash (Socket 1EA).SAMSUNG NAND Flash (Socket 1EA).SAMSUNG On eNAND (External Board, Opti on al).SAMSUNG 16Mbit SRAM 1EA.Dram port 0 : SAMSUNG 4 x 1Gb DDR2 SDRAM(x8).Dram port 1 : SAMSUNG 4 x 1Gb DDR2 SDRAM(x8) or SAMSUNG 4 x 2Gb DDR2SDRAM(x8)- TFT LCD & Touch panel in terface (External Board, default: 4.8” WVGA LMS480KF02)- ATA in terface (2 CF card sockets)- SD/SDIO/MMC in terface (3 SD Sockets)- Digital Video & Audio : HDMI 1.3 Video(720p) & S/PDIF 5.1 Channel Audio I/F- TV Out in terface ( Composite )- USB Host , USB OTG 2.0 in terface-High Speed SPI interface-IIS/AC97/PCM In terface : WM9713, WM8580 Audio CODEC on board- Gen eral Camera In terface : 2 port- MIPI Camera In terface :MIPI-CSI2 (1Gbps/La ne Serial Commu nicati on)- High Speed Serial MIPI In terface LCD :MIPI-DSI (1Gbps/La ne Serial Commu nicatio n)- Keypad in terface- Ether net In terface : DM9000(10/100Mbps Ethernet con troller) on board- 2 port UART in terface-JTAG port- Module Co nn ector (M1 M4).M1 (Module1): For GPS Daughter Board (UART, SPI) : Samsu ng GPD14B01(SiRFSTAR III GSD3) (Optio nal).M2 (Module2): For Mobile TV Daughter Board (SPI, IIC) or HD Radio (SPI, IIS)Mobile TV: Samsu ng S5P4F31 (TBD, Optio nal)HD Radio: SiPORT SD1010 (TBD, Optio nal) , Samsu ng (TBD, Optio nal).M3 (Module3): For Bluetooth Daughter Board (UART, PCM for PMIC Audio Codec).M4 (Module4): For Audio Daughter Board (AC97, IIS, IIC)2 SMDK S5PV210 REAL VIEWSMDK S5PV210 CPU BOARD REAL VIEWELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0ELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.05V/3MIPI-CSII IMIPI-DSI1! 1CFG3(CS)LCDI/FfKFlI iguJljffflCAMERA-A PortK.HDMI2: 疔! f 叶I.；丄ii巧亠丄一m i； /L 上 _kW-l 卑USB USB OTG HOSTCFG4(OM)dikS5PV210ViELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0ELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0Figure 2 S5PV210 CPU BOARD TOP VIEWELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0ELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0POWER RESETExter nalOn eNANDELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0ELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0SD/MMC SLOT 0SD/MMC2 3 4 Off(Switch Ope n)On (Switch Short)1. Select the Clock source(CFG4)Please refer to PLL CLOCK SOURCE SELECTION2. Select the Boot Device(storage) and set Boot Mode configuration switches (CFG4)Please refer to BOOT MODE SELECTION3. Set the CFG switch or Jumper for each booting device.External On eNAND- Check If OneNAND daughter card is connected onCON14 (on CPU board).- Set CFG36:1 to X0X010. (Xm0CS n4)CFG3CS5 CS45 4 321XOFF X CFFONOFFSet J2(o n CPU board) to 1-2 SHORT.J2SD/MMC or eMMCSet CFG22:1 to X0. (to use SDMMC channel 0 of S5PV210)CFG2 Description1()FFNAND FlashIn sert a NAND Flash toNAND socket (U4 on Baseboard).Set CFGB32:1 to 10. (Xm0CS n2)CFGB32 1ONOFFNOR FlashIn sert a NOR Flash to NOR socket (U3 on Baseboard).Set CFGB12:1 to 01. (Xm0CS n0)CFGB12 1OFFONSet CFGB72:1 to 00 and CFGB82:1 to 11 and CFGB92:1 to 00. ( to use SROM Addr 16:22)CFGB721OFFOFFCFGB82 1ON ONCFGB92 1OFF OFF4. Set CFGB13 for debugging message channel .UART ch2 is for default debuggi ng message cha nnel and boot ing cha nn el.(ch3 in case of EVT0)Connect to UART cable toCOM2 (CON15 on Base board)Set CFGB134:1 to 0001CFGB13 4321UART2 OFFOFFOFFON5. Check default Jumper setting.-JP140 Short- J41-2 short- J51-2 short-J82-3 short-JP41 Ope nJP1ShortJ1,J2Ope nELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0ELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.06. Connect 5V power adapter and push the power butt on.7. Check the Power LED if it is operating normally.Refer to LED description section.ELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0ELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.0ELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.04.1 PLL CLOCK SOURCE SELECTIONMain in put clock for the S5PV210 system can be selected by setti ng the XOM0 values.Descripti onCFG41 , (XOM0)24MHz X-tal Clock (XXTI)OFF24MHz X-tal Clock (XusbXTI)ON (default)4.2 BOOT MODE SELECTION4.2.1 Switch Co nfigurationDescriptionCFG46:2CFG46CFG45:2 CFG46CFG45CFG44CFG43CFG42I-ROMBooting sequence:StorageeSSD OFFOFFOFFOFFOFFNand 2KB, 5cycle(Nand 8bit ECC)ONNand 4KB, 5cycle(Nand 8bit ECC)ONOFFNand 4KB, 5cycle(Nand 16bit ECC)ONOnenandMux OFFONOFFOnenandDemuxONSD/MMC OFFONeMMC(4-bit)ONReservedONOFFOFFONNand 2KB, 4cycle(Nand 8bit ECC)ONNOR bootONOFFeMMC(8-bit)ONI-ROMBooting sequence:eSSD OFFONOFF OF:OFFNand 2KB, 5cycleONNote) If CFG46 is set to 1, It is used for debug mode that UART boot is first and USB boot is sec ond. UART boot has some ki nd of error case. In case of UART error, the iROM boot sequence moves to USB boot. USB boot also has some kind of error case like UART. If USB boot is fail, boot seque nce move to main storage boot.Please refer to iROM applicati on n ote which is more detail about error case.4.3 CONFIGURATION SWITCH DESCRIPTION IN CPU BOARD4.3.1 CFG3: SELECTION FOR CS#4,#5CFG3Descripti onCS5 CS465 4 321ONExter nalOneNandConn ect toBase CS#5External OneNandConn ect toBase CS#44.3.2 J2: SELECTIONfor In terrupt of Ext. On eNANDJ2 Descripti on1-2 shortConn ect to ONDXL_INT02-3 shortCo nn ect to ONDXL_INT1( default)4.3.3 CFG2: Configuration of MMC slot 0CFG2 Description1ON : MMC port 1 4bit Data WidthOFF : MMC port 0 8bit Data Width ( default)2ON : HDMI I2C Buffer DisableOFF : HDMI I2C Buffer En able4.3.4 CFG1: TSI I/FCFG3 Description1ONOFFTSI I/F Buffer En able:TSI I/F Buffer Disable2ON : TSI RXOFF : TSI TX4.3.5 J3: PSHOLD selectionJ3 Descripti on1-2 shortNot usi ng PSHOLDUsi ng PSHOLD.2-3 shortPSHOLD should be programmed Output-HIGH during pressing the power butt on ,.4.3.6 JP1: JIG ON selectionELECTRONICSSMDK-V210JJSEFS MANUAL_REV 0.04.4 CONFIGURATION SWITCH DESCRIPTION IN BASE BOARD4.4.1 CFGB1: SROM BANK0 CHIP SELECTORCFGB1 compo nent is used to select devices as SROM BUS I/F 0(B_Xm0CS n0).Descripti onCFGB12 1NOR (AMD) FlashOFFONSRAMONOFF4.4.2 CFGB2: SROM BANK1 CHIP SELECTORCFGB2 compo nent is used to select devices as SROM BUS I/F 1(B_Xm0CS n1).Descripti onCFGB22 1NOR (AMD) FlashOFFONSRAMONOFF4.4.3 CFGB3: SROM BANK2 CHIP SELECTORCFGB3 comp onent is used to select devices as SROM BUS I/F 2(B_Xm0CS n2/NFCS n0).Descripti onCFGB32 1SRAM OFFONNand CS 0ONOFF
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