AT89S51 中英文翻译

外文原文及中文翻译外文原文AT89S51The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. 1. Features： Compatible with MCS.-51 Products 4K Bytes of In-System Programmable (ISP) Flash Memory Endurance: 1000 Write/Erase Cycles 4.0V to 5.5V Operating Range Fully Static Operation: 0 Hz to 33 MHz Three-level Program Memory Lock 128 x 8-bit Internal RAM 32 Programmable I/O Lines Two 16-bit Timer/Counters Six Interrupt Sources Full Duplex UART Serial Channel Low-power Idle and Power-down Modes Interrupt Recovery from Power-down Mode Watchdog Timer Dual Data Pointer Power-off Flag Fast Programming Time Flexible ISP Programming (Byte and Page Mode) Green (Pb/Halide-free) Packaging Option2.DscriptionThe AT89S51 provides the following standard features:4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. 3.Pin Description: VCC：Supply voltage (all packages except 42-PDIP). GND：Ground (all packages except 42一PDIP; for 42-PDIP GND connects only the logic core and the embedded program memory). VDD：Supply voltage for the 42-PDIP which connects only the logic core and the embedded program memory. PWRVDD：Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers. The application board MUST connect both VDD and PWRVDD to the board supply voltage. PWRGND：Ground for the 42一PDIP which connects only the I/O Pad Drivers. PWRGND and GND are weakly connected through the common silicon substrate, but not through any metal link. The application board MUST connect both GND and PWRGND to the board ground. Port 0：Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high一impedance inputs.Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, PO has internal pull-ups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification. Port 1：Port 1 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull一ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (lip) because of the internal pull一ups. Port 2：Port 2 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull一ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (lip) because of the internal pull一ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, Port 2 uses strong internal pull一ups when emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3：Port 3 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull一ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (lip) because of the pull-ups.Port 3 receives some control signals for Flash programming and verification.Port 3 also serves the functions of various special features of the AT89S51，as shown in the following table. RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled. ALE/PROG：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may beused for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN：Program Store Enable (PSEN) is the read strobe to external program memory.When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at OOOOH up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to Vcc for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming. XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2：Output from the inverting oscillator amplifier 4.Special Function Registers：Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1 s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Interrupt Registers:The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register. Dual Data Pointer Registers:To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DPO at SFR address locations 82H-83H and DP1 at 84H-85H.Bit DPS=0 in SFR AUXR1 selects DPO and DPS=1 selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register. Power Off Flag:The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to 1”during power up. It can be set and rest under software control and is not affected by reset. 5.Memory Organization：MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed. Program Memory：If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51，if EA is connected to Vcc, program fetches to addresses OOOOH through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory. Data Memory：The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space. 6.Watchdog Timer (One-time Enabled with Reset-out)：The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14一bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01 EH and OE1 H in sequence to the WDTRST register (SFR location OA6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin. 7.Timer 0 and 1：Timer 0 and Timer 1 is a 16-bit Timer/Counter.8.Interrupts:The AT89S51 has a total of five interrupt vectors:two external interrupts,two timer interrupts,and the serial port interrupt.These interrupts are all shown in Figure 8.1.Each of these interrupt sources can be individually enabled or disabled by setting or chearing a bit in Special Function Register IE.IE also contains a global disable bit,EA,which disables all interrupts at once.Note that Table 8.1 shows that bit positions IE.6 and IE.5 are unimplemented.User software should not write 1s to these bit positions,since they may be used in future AT89 products.The Timer 0 and Timer 1 flags, TF0 and TF1,are set at S5P2 of the cycle in which the timers overflow.The values are then polled by the circuitry in the next cycle.Table 8.1:Interrupt Enable(IE) RegisterFigure 8.1:Interrupt Sources9.Idle mode:In idle mode ,the CPU puts itself to sleep while all the on-chip peripherals remain active.The mode is invoked by software.The content of the on-chip RAM and all the special function registers remain unchanged during this mode.The idle can be terminated by any enabled interrupt or by a hardware reset.中文翻译AT89S51 AT89S51是美国ATMEL公司生产的低功耗，高性能CMOS 8位单片机，片内含4k bytes的可系统编程的Flash只读程序存储器，器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准8051指令系统及引脚。它集Flash程序存储器既可在线编程（ISP)也可用传统方法进行编程及通用8位微处理器于单片芯片中，ATMEL公司的功能强大，低价位AT89S51单片机可为您提供许多高性价比的应用场介，可灵活应用于各种控制领域。 1.主要性能参数： 与MCS-51 产品指令系统完全兼:容 4k字节在线系统编程(ISP) Flash闪速存储器 1000次擦写周期 4. 0-5. 5V的工作电压范围 全静态工作模式：0Hz-33MHz 三级程序加密锁 1288字节内部RAM 32个可编程I/O口线 2个16位定时/计数器 6个中断源 全双工串行UART通道 低功耗空闲和掉电模式 中断可从空闲模式唤醒系统 看门狗(WDT)及双数据指针 掉电标识和快速编程特性 灵活的在线系统编程(ISP一字节或页写模式) 2.功能特性概述： AT89S51提供以下标准功能：4k字节Flash闪速存储器，128字节内部RAM， 32个I/O口线，看门狗（WDT），两个数据指针，两个16位定时/计数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89S51可降至0Hz的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时/计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。引脚功能说明：3.引脚功能 Vcc： 电源电压 GND：地 P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复用口。作为输出口用时，每位能驱动8个TTL逻辑门电路，对端口写1可作为高阻抗输入端用。 在访问外部数据存储器或程序存储器时，这组口线分时转换地址(低8位)和数据总线复用，在访问期间激活内部上拉电阻。 在Flash编程时，P0 口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。 P1口：P1是一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对端口写1，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，囚为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流(In)。 Flash编程和程序校验期间 P 1接收低8位地址。 P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对端口写1，通过内部的上拉电阻把端口拉到高电平，此时可作输入口，作输入口使用时，囚为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流(In)。在访问外部程序存储器或16位地址的外部数据存储器(例如执行MOVX DPTR指令)时，P2口送出高 8位地址数据。在访问8位地址的外部数据存储器(如执行MOVX Ri指令)时，P2口线卜的内容(也即特殊功能寄存器（SFR)区中P2寄存器的内容)，在整个访问期间不改变。 Flash编程或校验时，P2亦接收高位地址和其它控制信号。 P3口：P3口是一组带有内部上拉电阻的8位双向I/O口。P3口输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对P3 口写入“1”时，它们被内部上拉电阻拉高并可作为输入端口。作输入端时，被外部拉低的P3 口将用上拉电阻输出电流（In）。P3口除了作为一般的I/O口线外，更重要的用途是它的第二功能。P3 口还接收一些用于Flash闪速存储器编程和程序校验的控制信号。第二功能如下表：P3口引脚第二功能P3.0RXD（串行输入）P3.1TXD（串行输出）P3.2/INTO（外部中断0输入）P3.3/INT1（外部中断1输入）P3.4T0（定时/计数器0外部输入）P3.5T1（定时/计数器1外部输入）P3.6/WR（外部数据存储器写信号）P3.7/RD（外部数据存储器读信号）RST：复位输入。当振荡器工作时，RST引脚出现两个机器周期以上高电平将使单片机复位。WDT溢出将使该引脚输出高电平，设置SFR AUXR 的DISRTO位（地址8EH）可打开或关闭该功能。DISRTO位缺省为RESET输出高电平打开状态。 ALE/PROG：当访问外部程序存储器或数据存储器时，ALE(地址锁存允许)输出脉冲用于锁存地址的低8位字节。即使不访问外部存储器，ALE仍以时钟振荡频率的1/6输出固定的正脉冲信号，囚此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲。对Flash存储器编程期间，该引脚还用于输入编程脉冲（PROG）。如有必要，可通过对特殊功能寄存器（SFR)区中的8EH单元的D0位置位，可禁正ALE操作。该位置位后，只有一条MOVX和MOVC指令ALE才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE无效。 PSEN：程序储存允许(PSEN)输出是外部程序存储器的读选通信号，当AT89S51由外部程序存储器取指令(或数据)时，每个机器周期两次PSEN有效，即输出两个脉冲。当访问外部数据存储器，没有两次有效的PSEN信号。 EA/VPP：外部访问允许。欲使CPU仅访问外部程序存储器(地址为0000H-FFFFH), EA端必须保持低电平(接地)。需注意的是：如果加密位LB1被编程，复位时内部会锁存EA端状态。如EA端为高电平(接Vcc端)，CPU则执行内部程序存储器中的指令。Flash存储器编程时，该引脚加上+12 V的编程电压Vpp。 XTAL 1：振荡器反相放大器及内部时钟发生器的输入端。 XTAL2：振荡器反相放大器的输出端。 4.特殊功能寄存器： 特殊功能寄存器的于片内的空间分布的这些地址并没有全部占用，没有占用的地址亦不可使用，读这些地址将得到一个随意的数值。而写这些地址单元将不能得到预期的结果。 中断寄存器：各中断允许控制位于IE寄存器，5个中断源的中断优先级控制位于IP寄存器。 双时钟指针寄存器： 为更方便地访问内部和外部数据存储器，提供了两个16位数据指针寄存器：DP0位于SFR(特殊功能寄存器)区块中的地址82H, 83H和DP1位于地址84H, 85H，当SFR中的位DPS=0选择DP0，而DPS=1则选择DP1。用户应在访问相应的数据指针寄存器前初始化DPS位。 电源空闲标志： 电源空闲标志（POF）在特殊功能寄存器SFR中PCON的第4位(PCON.4)，电源打开时POF置1，它可由软件设置睡眠状态并不为复位所影响。5.存储器：51系列单片机的程序和数据存储器具有独立的地址空间，最大有64K字节的外部程序和数据存储器。程序存储器： 如果EA引脚接地(GND)，全部程序均执行外部存储器。在AT89S51,假如EA接至Vcc(电源+)，程序首先执行地址从0000H-OFFFH （4KB）内部程序存储器，而执行地址为1000H-FFFFH (60KB)的外部程序存储器。 数据存储器：AT89S51的具有128字节的内部RAM，这128字节可利用直接或间接寻址方式访问，堆栈操作可利用间接寻址方式进行，128字节均可设置为堆栈区空间。 6.看门狗定时器(WDT)：WDT是为了解决CPU程序运行时可能进入混乱或死循环而设置，它由一个14bit计数器和看门狗复位SFR (WDTRST)构成。外部复位时，WDT默认为关闭状态，要打开WDT，用户必须按顺序将01EH和0E1H写到WDTRST寄存器（SFR地址为OA6H,当启动了WDT，它会随晶体振荡器在每个机器周期计数，除硬件复位或WDT溢出复位外没有其它方法关闭WDT，当WDT溢出，将使RSF引脚输出高电平的复位脉冲。 7.定时器0和定时器1：定时器0和1都是16位定时/计数器。8.中断： AT89S51具有的五个中断源：两个外部中断，两个定时器中断，一个串口中断，如图8.1所示。 这些中断源的每一个都可以通过设置特殊功能寄存器IE启用或禁用，IE还包含了一个全局禁止位EA，它可一次禁止所有的中断。 请注意，表8.1中位IE.6和IE.5是保留位，它们可能会在未来的AT89产品中使用。 表8.1：中断允许寄存器（MSB）(LSB)EA-ESET1EX1ET0EX0中断允许位=1，允许中断；中断允许位=0，不允许中断。EAIE.7总中断允许控制位-IE.6保留-IE.5保留ESIE.4串行口中断允许控制位ET1IE.3定时/计数器1的中断允许控制位EX1IE.2外部中断1的中断允许控制位ET0IE.1定时/计数器0的中断允许控制位EX0IE.0外部中断0中断允许控制位图8.1.：中断源 9.空闲模式： 在空闲模式下，CPU使自己进入睡眠状态，而所有片上外设仍然工作.此模式由软件触发，片内RAM和特殊功能寄存器的所有内容保持不变.此模式可被任何使能中断或硬件复位终止。