veriloghdl电子时钟实验报告

电子时钟：电子时钟的功能：可以显示时间，还可以修改时间。结构图NO.7：此电路适合于设计时钟、定时器、秒表等。因为可利用键8和键5分别控制时钟的清零和设置时间的使能；利用键7、5和1进行时、分、秒的设置。实验代码：模块一：时间显示/clk:秒功能的时钟信号，为1Hz的脉冲信号/time_set_en:时间设置使能信号/time_clear(键8)：时钟显示的清零/hourh_set,hourl_set,minh_set,minl_set,sech_set,secl_set:设置后的小时、分、秒/hourh,hourl:小时的高低位/minh,minl:分的高低位/sech,secl:秒的高低位/cout:进位输出，即计满24小时，向天产生的进位输出信号module time_count(clk,time_set_en,time_clear,hourh_set,hourl_set,minh_set,minl_set,sech_set,secl_set,hourh,hourl,minh,minl,sech,secl);input clk;input time_set_en,time_clear;input3:0hourh_set,hourl_set,minh_set,minl_set,sech_set,secl_set;output3:0hourh,hourl,minh,minl,sech,secl;reg3:0hourh,hourl,minh,minl,sech,secl;reg c1,c2; /c1和c2分别为秒向分，分向时的进位always(posedge time_set_en or posedge clk or posedge time_clear) begin if(time_set_en) /time_set_en:时间设置使能信号 begin sech=sech_set; secl=secl_set; minh=minh_set; minl=minl_set; hourh=hourh_set; hourl=hourl_set; end else if(time_clear) /time_clear(键8)：时钟显示的清零 begin hourh=0; hourl=0; minh=0; minl=0; sech=0; secl=0; end else begin if(secl=9) /sech,secl:秒的高低位设置 begin secl=0; if(sech=5) begin sech=0; c1=1; if(minl=9) /minh,minl:分的高低位设置 begin minl=0; if(minh=5) begin minh=0; c2=1; if(hourh=2)&(hourl=3) begin hourh=0; hourl=0; end if(hourl=9) /hourh,hourl:小时的高低位设置 begin hourl=0; if(hourh=2) hourh=0; else hourh=hourh+1; end else begin hourl=hourl+1; end end else begin minh=minh+1; end end else begin minl=minl+1; c2=0; end end else begin sech=sech+1; end end else begin secl=secl+1; c1=0; end end endendmodule模块二：时间设置/key7:设置数码管8和7/key4:设置数码管5和4/key1:设置数码管2和1/time_set_en(键5)：设置时间的使能端/hourh_set,hourl_set,minh_set,minl_set,sech_set,secl_set:设置后的小时、分、秒/hourh,hourl,minh,minl,sech,secl:当前的小时，分，秒module time_set(key7,key4,key1,time_set_en,hourh,hourl,minh,minl,sech,secl,hourh_set,hourl_set,minh_set,minl_set,sech_set,secl_set);input key7,key4,key1;input time_set_en;input3:0hourh,hourl,minh,minl,sech,secl;output3:0hourh_set,hourl_set,minh_set,minl_set,sech_set,secl_set;reg3:0hourh_set,hourl_set,minh_set,minl_set,sech_set,secl_set;always(posedge time_set_en) begin if(key7) begin if(hourh_set=2)&(hourl_set=3) begin hourh_set=0; hourl_set=0; end else if(hourl_set=9) begin hourl_set=0; if(hourh_set=2) hourh_set=0; else hourh_set=hourh_set+1; end else begin hourl_set=hourl_set+1; end end else if(key4) begin if(minl_set=9) begin minl_set=0; if(minh_set=5) begin minh_set=0; end else minh_set=minh_set+1; end else begin minl_set=minl_set+1; end end else if(key1) begin if(secl_set=9) begin secl_set=0; if(sech_set=5) begin sech_set=0; end else sech_set=sech_set+1; end else secl_set=secl_set+1; end else begin hourh_set=hourh; hourl_set=hourl; minh_set=minh; minl_set=minl; sech_set=sech; secl_set=secl; end endendmodule模块三：顶层模块/clk:时间计数的时钟信号/time_set_en:设置时间使能信号/time_clear:显示时间清零使能信号/hourh,hourl,minh,minl,sech,secl:当前或设置后的小时，分，秒/key7:设置数码管8和7/key4:设置数码管5和4/key1:设置数码管2和1module time_and_set(clk,time_set_en,time_clear,hourh,hourl,minh,minl,sech,secl,key7,key4,key1);input clk;input time_set_en,time_clear;input key7,key4,key1;output3:0 hourh,hourl,minh,minl,sech,secl;wire3:0hh,hl,mh,ml,sh,sl;wire3:0hh_set,hl_set,mh_set,ml_set,sh_set,sl_set;time_count U1( .clk(clk),.time_set_en(time_set_en),.time_clear(time_clear),.hourh_set(hh_set),.hourl_set(hl_set),.minh_set(mh_set),.minl_set(ml_set),.sech_set(sh_set),.secl_set(sl_set),.hourh(hourh),.hourl(hourl),.minh(minh),.minl(minl),.sech(sech),.secl(secl);time_set U2(.key7(key7),.key4(key4),.key1(key1),.time_set_en(time_set_en),.hourh_set(hh_set),.hourl_set(hl_set),.minh_set(mh_set),.minl_set(ml_set),.sech_set(sh_set),.secl_set(sl_set),.hourh(hourh),.hourl(hourl),.minh(minh),.minl(minl),.sech(sech),.secl(secl);endmodule模块一的时序仿真图：RTL图：引脚图：实验体会：通过这次课程设计，对fpga有了很多的的认识，而且懂得了硬件的更多知识，课程设计过程中，总会遇到很多的问题，然后一起跟同学讨论，或者问老师，解决问题之后感觉收获很多，而且学会了自己独立思考，查询资料。