ICT测试原理及程式简介ppt课件

按一下以編輯母片標題樣式,按一下以編輯母片,第二層,第三層,第四層,第五層,*,ICT,測試原理及程式簡介,EPDVIII ICT,Randy .,xiang,一,.ICT,的功能,ICT也叫在線測試儀，是一台靜態元件測試儀，它能准確，高速地測量PCB上已裝元件的不良問題，包括元件的漏件，錯件，裝反，空焊，來料不良，PCB上金道之間的開短路等。可測元件包,括：電阻，電容，二極管，三極管，電感，變壓器，,IC,等絕大多數電子元件。,二,. ICT,的硬件結構,ICT包括ICT系統主機，電腦系統，壓床，測試治具。其中ICT系統主機包括：電源部分，量測控制板，I/O卡，DC量測板，AC量測板，開關板，HP-JET量測板，高壓量測板(選配件)。,公司,: TRI (Test Research Inc.),德律科技,產地,:,台灣,工作條件,治具類型,:,真空治具,.,真空壓力,:,最小,56cmHg.,外部真空管,2,根,.,氣壓,: 4kg/cm2,6kg/cm2.,氣壓管,1,根,.,操作溫度,: 0,。,C,30,。,C.,環境濕度,: 25% RH-75%RH.,最小工作空間,:,深：,1.5,公尺。,寬：,2.0,公尺。,高：,2.0,公尺。,TRI 8001,測試畫面,公司,: TRI (Test Research Inc.),德律科技,產地,:,台灣,工作條件,電源,:3 AC 220V-245V, 50/60 Hz5%,氣壓,: 4,6KGF,CM2,TRI 518,測試操作畫面,相匹配的治具簡介,相匹配的治具必需為真空治具,即治具下壓的動力為真空,.,真空治具根據繞線長度分為,:,長線治具,短線治具和無線治具,.,我們現在使用的治具為長線治具,.,治具內部結構如下,:,SENSOR,壓棒,探針,彈簧,密封墊,氣管,油壓撐竿,雙絞線繞線,BUFFER BOARD,Interface,Introduction of,Agilent,3070,Agilent 3070 Family,307X, up to 5200 nodes,327X, up to 1300 nodes,317X, up to 2600 nodes,Anatomy of the Agilent Medalist 3070,Agilent 3070 Hardware,Agilent 3070,Electronics Cabinet,DUT power suppliesExternal Instruments,Testhead,Flat Screen Monitor on moveable arm. Keyboard on moveable arm.,End Cabinet contains,Computer, Power Distribution Unit, Testhead rotation switch.,Testhead,Test Fixture Emergency Power Off Switch,Test Fixture,Mother Board,(one per bank),Module power Supplies,Agilent3070,測試畫面,Anatomy of the Agilent Medalist i3070,Fixture,Probe to Pin Wiring,Test Probe,Support Plate,Probe Plate,Personality Pin,Alignment Plate,Printed Circuit Board,Fixture Frame,Vacuum Gasket,R1,Stimulus,Response,Anatomy of the Agilent Medalist 3070,Agilent 3070 TestHead,Bank 2 Bank 1,Module 2 Module 0,Module 3 Module 1,Slot 1,Slot 1,Slot 1,Slot 1,Slot 1: ASRU,Slot 6: Module Control CardAll others: Pin Cards,Pin 78 - 1,Pin 1 - 78,Fixture Numbering,BRC: Bank Row Column,Bank 2 Bank 1,Module 2,Module 3,Module 0,Module 1,Slot 1: ASRU,Slot 6: Control,Slot 1: ASRU,Slot 6: Control,Slot 1: ASRU,Slot 6: Control,Slot 1: ASRU,Slot 6: Control,MOTHER BOARD,MOTHER BOARD,Row 1,Row11,Row 13,Row 23,Row 1,Row11,Row 13,Row 23,Column 78 1 78 1,1A at:,2 20 61,CLOCK_ENABLE at:,2 18 48,Double Density node at:,2 20 1 61,Bank 1 Node:,1 18 48,Anatomy of the Agilent Medalist 3070,The Module Control Cards,The Analog Stimulus - Response Unit (ASRU),Agilent 3070 Module,Mother,card,ASRU card,Control card,Pin card,Slot 1,Slot 2,Slot 3,Pin card,Slot 4,Slot 8,Slot 6,Slot 7,Slot 5,Slot 9,Slot 10,Slot 11,Pin card,Pin card,Pin card,Pin card,Pin card,Pin card,Pin card,Module card configuration,ASRU Card,提供模拟激励信号,使用测量运算放大器进行反馈信号的测量,提供上电测试的电源通道,配在每个模块第,1,号插槽,Module Control Card,控制实际的测试过程,2,个,rcvc,测试频率,带有,8,个通用开关,(GP Relay),配在每个模块的第,6,号插槽,MUX,S I A B L G,MOA,Detector,Aux,Source,Hybrid Double Density,Channel A,Channel B,. . . . . . . . . . . .,Channel H,Pin Card,X1.X8 XG XL,Analog Subsystem,Digital Subsystem,9:2,R1,ASRU,Hybrid 32 Card,Channel 0,Channel 8,. . . . . .,6:2,Pin Card,X1.X8 XG XL,Digital Subsystem,3:2,MUX,S I A B L G,MOA,Detector,Aux,Source,Analog Subsystem,ASRU,ICT,TEST,程式,与,夾具,命名規則,1.ICT,程式命名規則,設備型號,T(TR8001,TR518),A(Agilent,3070),T,A+ P/N+EC,+,夾具套數,2.ICT,夾具命名規則,設備型號,T,A+P/N+,夾具套數,MHS,机种为例：,P/N,：,69Y4784 EC:N31078R,ICT,程式命名,:,A90Y4784N31078R_01,ICT,程式命名,:A90Y4784_01,三,. ICT,的基本測試原理,1.,隔離量測原理,ICT其實是一台高級的萬用表，但它具有隔離(GUARDING)功能，這是它不同于萬用表的最大特點。GUARDING的作用是使一個被測元件在測試時不受旁路元件的影響，而萬用表做不到這一點。在 ICT 內部電路中利用一顆 OP放大器 當做一個隔離點（最多可有五個隔離點），如果是:,source: Overview of 3070 Test,UnpoweredTests,Shorts,Analog Incircuit,VTEP/TestJet,PoweredTests,Setup PowerSupplies,Digital Incircuit,Analog Powered,Pins,Other Powered,Part 3,Pins Test,Pins,测试概述,ICT,测试的原理要求夹具的探针和电路板的测试点,(testpad),要有良好的电气接触,.,Pins,测试就是在测试正式开始前验证探针和测试点,有无,接触的工序,.,Pins,测试只定性验证有无接触，,pins pass,是最低要求，并不能保证接触良好,.(,绕线出现错误；,pins,接触不好，阻抗大，但依然有,current flow;,隔离点,无法 测,),Pins Test,“,A”,“,B”,“,C”,“,D”,“,E”,“,F”,“,G”,“,Node_Names”,+,2.5V,10K,DVM,S,Node E has no current flow. It is capacitively isolated and cannot be tested in Pins Test.,Pins Test - Syntax,nodes Anodes Bnodes Cnodes D!nodes E” ! node capacitively isolatednodes ”Fnodes ”G,Pins Test Called from testplan,Pins test,的预定义,sub Set_Custom_Option,global Off, Pretest, Failure,！设置全局常量,global Chek_Point_Mode,Chek_Point_Mode=Pretest,!choose Off, Pretest, Failure,！选择,pins,测试模式，,off,不进行,pins,测试,！,pretest,在其它测试前进行,pins,测试,！,failure,其它测试,fail,后，进行,pins,测试,end sub,Pins,测试的调试,Pins,测试中的节点排列顺序不影响测试结果,Pins,测试中没有其他测试选项,所以,pins,测试只有,node,的取舍,哪些节点,pins,不可测,?,电容阻隔的点（,capacitively isolated,）,IPG,自动注释,只连到,IC,的,NC,脚的 ,IPG,自动注释,所连器件在板上都没有放,(no pop),的 手动确认,Part 4,Shorts Test & Opens Test,L201,L201-1,L201-2,100 ohms,DVM,0.1V,Shorts Test overview,Shorts Test,! IPG: rev B.03.60 ,threshold 12,settling delay 50.00u,settling delay 525.0u,short “L201-1” to “L201-2”,settling delay 50.00u,short “J201-1” to “J201-2”,. . .,threshold 1000,. . .,nodes “Data7”nodes “R201-2”nodes “R201-1”,. . .,threshold 8,. . .,nodes “R202-2”nodes “R202-1”nodes “GND”,DVM,L201,Series Resistance = 6ohms,R202 at 33ohms,DVM,R201 at 20k,L201-1,L201-2,R201-1,R201-2,R202-1,R202-2,Expected Shorts,L201,L201-1,L201-2,100 ohms,DVM,0.1V,如图，对,L201,进行,shorts,测试，预期为短路。,a).,设置阀值为,12,欧姆，如果,R,测量,12(threshold),，,则测试,pass,，反之，,fail,。,b).,设置从加信号到开始测量的延时，以致等待信号稳定。,c).,测量两个节点之间的阻值，并判断！,语法如下：,! In the “shorts” file !,! Syntax !,! short “Node_1” to “Node_2” !,threshold 12,Settling delay 50u,Settling delay 525u,Shorts “L201-1” to “L201-2,Shorts Test (Good Board)Testing For Shorts,100mV,100,W,“,A”,“,B”,“,C”,“,D”,“,E”,“,F”,“,G”,“,Node_Names”,Shorts Test (Bad Board)Testing For Shorts,100mV,100,W,“,A”,“,B”,“,C”,“,D”,“,E”,“,F”,“,G”,?,Which node is shorted to node C?,A short has been detected from node C to one of the remaining nodes D, E, F or G,Shorts Test (Bad Board)Testing For Shorts,100mV,100,W,“,A”,“,B”,“,C”,“,D”,“,E”,“,F”,“,G”,?,Which node is shorted to node C?,A short has been detected from node C to one of the remaining nodes D, E, F or G,Node C is,not,shorted to nodes D and E,Node C is shorted to either nodes F or G,Node C may be shorted to node G,This is not assumed!,Node C is shorted to node G,假象短路的调试,假象短路出现的原因是特定的节点的测试顺序造成误判,必须在程序发布前排除,方法是将出错的节点（或者节点群）挪到被短路的节点,(,或节点群）后面。这个过程在调试中可能要重复几次,挪动时最好在同一个,threshold,设置群之内,.,可以自己设置,threshold,，但是要遵循,threshold,值从大到小的顺序, Threshold,最低尽量不要设到,4,以下，尤其是电源点。否则会有漏掉真正短路的可能,.,不要轻易把节点放到测试文件的末尾，这样可能造成开短路 覆盖率的缺失，尤其是电源点或者,VCC,这类本身就是低阻抗的节点,.,调试时,settling delay,可以加的比较大，在优化时再减小,Shorts Test - Report Options,report common devices,report limit 12,Short #1From: D3 22044To: D4 21938Common Devices: U1 U4,report netlist, common devicesreport limit 12,Short #1From: D3 22044 u1.5,u4.3 u5.2 u7.5To: D4 21938 u1.8,u4.4 u6.2 u2.10 Common Devices: u1 u4,report phantoms,Short #1From: D3 22044To: D4 21938,Part 5,Analog Test,capacitors,connectors,diodes,FETs,fuses,inductors,jumpers,resistors,switches,transistors,zeners,Part 6,Testjet & VTEP & iVTEP,The VTEP/iVTEP/TestJet Test,BGA with floating metal tops/heat spreaders are testable!,PCB,AC,Signal,Ground,VTEP Sensor plate,C measured,Electronics board,(Amplifier),To MultiplexCard,Metal BGA Under-Test,Floating,Metal Top,TestJet,测试能力的极限值为,20fF,，,VTEP,测试能力的极限值为,5fF,。,低于,5,的值使用,iVTEP,来进行测试，但是,iVTEP,的测试速度比较慢，而且不能用来测试连接器。,Bar = Num Pins in Range,0,5,10,15,20,25,30,0 to 5,5 to 10,10 to 15,15 to 20,20 to 25,25 to 30,30 to 35,35 to 40,40 to 45,45 to 50,TestJet limit,Measurement (in fF),VTEP limit,1.27 mm pitch,593 Solder Balls,0.8mm pitch,1202 SB,TestJET,和,VTEP,的测试界限,Aug, 2010,The VTEP/TestJet Verification,The TestJet Test,default threshold low 20 high 10000,device “u1” test pins 1 test pins 2, 3 test pins 4, 5, 6,!,test pins 7 ! Ground pins commented by IPG test pins 8 test pins 13,!,test pins 14 ! Fixed pins commented by IPG,device “u2” bottom;,test pins 1 test pins 2 .,Turn On AutoDebug for iVTEP + VTEP,AutoDebug calculates the threshold limit,Before ADB,After ADB,The TestJet Test - After Debug,default threshold low 20 high 10000,device “u1”; threshold low 15 high 10000,test pins 1 test pins 2, 3,; threshold low 350 high 10000,test pins 4, 5, 6,; threshold low 450 high 10000,! test pins 7 ! Ground pins commented by IPG test pins 8 ,! test pins 13 ! Test measures 9,test pins 8 test pins 14 ! Fixed pins commented by IPG,device “u2” bottom;,test pins 1,; threshold low 15 high 10000,test pins 2,test pins 3,; threshold low 40 High 10000,.,Part 10,Overview of Boundary-Scan,Test Data,In (,TDI,),Test Data,Out (,TDO,),Typical IC with Boundary-Scan,Boundary,Cells,Core,Logic,Test Data,In (,TDI),Test Data,Out (,TDO,),Test Mode,Select (,TMS,),Test Clock,(,TCK,),TEST ACCESS PORT,CONTROLLER,(TAP),The device can be controlled,and tested through TDI, TCK,TMS, & TDO,Arrows denote access points,Basic Test of IC with Boundary-Scan,Test Data,In (,TDI,),Test Data,Out (,TDO,),Do not need to understand the,Device Function (Core Logic),Scan data in TDI to Output cells.Tester verifies data on outputs.,Tester applies Data on inputs. Cellscapture data on inputs. Datascanned out TDO for verification.,The Boundary-Scan Test Development Process,Start with the BSDL file,BSDL means ,B,oundary-,S,can,D,escription,L,anguage”,A language for describing the device specific characteristics of 1149.1 devices,Language subset of VHDL,Who will write BSDL,ASIC designers,Semiconductor vendors,Test engineers,Typical IC with Boundary-Scan,Test Data,In (,TDI),Core,Logic,TMS = Serial,Test Clock,(,TCK,),TEST ACCESS PORT,CONTROLLER,(TAP),010101010101,1,0,1,0,1,0,0,1,0,1,0,1,0,1,0,1,0,1,TMS = Parallel,TMS = Parallel,Typical IC with Boundary-Scan,Test Data,In (,TDI),Core,Logic,TMS = Serial,Test Clock,(,TCK,),TEST ACCESS PORT,CONTROLLER,(TAP),0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,101010,Thank you!,&,More Questions ?,