第九章功能验证

,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,Click to edit Master title style,第九章,功能验证,Outlines,What is Verification?,Problem and Trend of Function Verification,HW/SW Co-verification,Emulator based co-verification,ESL design tool based co-verification,Assertion Based Verification(ABV),What is Verification?,Design concept verification(functionality verification),Does the behavioral idea work as expected?,Design implementation verification,Does the physical design behave as expected?,Design performance verification,How fast the chip can operate correctly?,How much power the chip consumes?,Fault simulation,Will the selected test vector cover design and manufacturing faults?,Silicon chip testing,Does the silicon chip work and operate as expected?,Problem of Function Verification,Functionality Verification has been over 60%(even 70%)of design cycle for millions gates design.,30%-70%manpower for verification,CPU time increases exponentially in big design,Problem of Function Verification-cont.,Most of the verification time is spent doing debug,Hardware/software interactions,Analog/digital interactions,Testbenchs,IC design focus on RTL verification only,Software development after IC is ready,Verification can never finished!,(example:,a chip from CL company,ARM+DSP Based Portable Audio Decoder,spend 3 yrs design,tapeout,6 times,but never on production,),Trend of Function Verification,New methodologies and better tools,Understand system context,Hardware/software co-verification,Locate root cause of problems easily,Assertion based verification,Outlines,What is Verification?,Problem and Trend of Function Verification,HW/SW Co-verification,Emulator based co-verification,ESL design tool based co-verification,Assertion Based Verification(ABV)Methodology,Hardware/Software Co-verification,System components,Not just Hardware,RTOS,Software,Analog,Environment,Verification of complete system both HW/SW,Hardware/Software Co-verification,HW/SW co-verification is a methodology that enables the execution of,embedded system software,on a simulated representation of the,system hardware,Emulator based co-verification(emulation),ESL based co-verification,Emulation,Emulation is a method of modeling the design in hardware,Emulation dominated by FPGA-based system,Co-Emulation,Integrating simulation and emulation environments for co-verification.,Providing an in-circuit verification environment.,Providing a system-level testing environment.,Providing a system prototyping.,Co-verification with ESL Design tool,Done in early design stage,More flexible,Less expensive,Outlines,What is Verification?,Problem and Trend of Functional Verification,HW/SW Co-verification,Emulator based co-verification,ESL design tool based co-verification,Assertion Based Verification(ABV)Methodology,What is assertion,Assertion in simulation,Assertion in formal verification,Assertion Based Verification(ABV),Why need assertion based verification?,What is assertion based verification?,Current Practices of Function Verification,HDL,simulation where engineers write“reactive,testbenches,”,Check waveform,code coverage,then write more patterns,Input generation,Manual(verification engineers think of test cases),Usually or block level verification,Pseudo-random,Need auto-,testbench,tool,need to have accurate model at abstract level,Need input constraints to limit to legal vectors,Normally for chip level verification,Mixed(some random parameters),Need to write a lot of vectors to get enough“coverage”!,Current Practices cont.,Low,controllability,(cant generate enough vectors).,Low,observability,(internal errors might not propagate during test).,Doesnt facilitate reuse.,Trend of Function Verification,Smarter simulation,Properties,Accelerated simulator,coverage tool,Static formal verification,Start from reset state,looking for proof,Dynamic formal verification(or model checking,property checking,hybrid formal verification),Start from simulation result,prove whether a property is hold under the simulation.Looking for counterexamples,Assertion based verification methodology,Assertions are statements about how the design is intended to behave at the RTL level or higher abstraction level,simulation based verification,Formal verification w,ith advanced hybrid formal tool,Assertion-Based Verification(ABV),Convergence of design and verification to create an improved design-for-verification methodology.,Assertion,Assertion is a precise description of what behavior is expected when a given input is presented to design.,used as monitors/checker looking for bad behavior during verification,used to create an alert for desired behavior,Assertion Based Verification(AVB),Assertions,must be written in design code(C like system abstraction model or RTL)or,testbench,(Establish assertions)as an enabler of much more efficient verification,simplified analysis,and the synergistic use of simulation and formal verification methods.,Assertion in simulation,Can be used