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单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,2012/2/26,#,DDR/DDRIIThings to consider,1,Objectives,This presentation covers aspects not addressed in DDR SDRAM Megawizard demonstration.,Aims to help answers questions like,How many controllers can I get in this device,What do I need to consider at layout,What if I want to run below 100 or above 200 MHz,Are there additional considerations for Hardcopy,Where can I find more information,Etc etc,Unfortunately this does make the presentation “bitty”.,2,What is DDR? (Brief),(This section for those at the beginning of the learning curve.),3,What is DDR,DDR stands for “double data rate”.,Generally when people talk about DDR they are talking about transferring data to and from memory.,DDR simply means there is data on both edges of the strobe.,Data Strobe (dqs),Data (dq),4,Why would I use it?,To increase your bandwidth for the same number of pins (compared to SDRAM).,And because it is cheap (commercial part used in PCs).,Your customers use it. Look at the market share of DDR and DDR2,Source: Gartner Dataquest (May 2004),What is involved?,Data passes backwards and forwards on a high speed bi-direction bus. A data strobe (DQS) travels with the data.,DDR2,Memory,Memory,Controller,On-Chip DLL Phase Shift,for DQS Delay Circuitry,t,DQ_i,DQS_i,DQ,DQS,DQ,Read Operation,DQS,6,What is involved,The FPGA must align the data and strobe (dq and dqs) on the way out (writes) and delay the strobe (dqs) by 90 degrees on the way in (reads) to use dqs as capture strobe.,The operation clearly involves going “off chip” so we need to be careful of timing analysis.,And it is (or can be) high speed so we need to watch out for things like termination.,7,Where can I find more information?,(All: Rejoin presentation here),8,What collateral already exits?,The Memory Solutions Webpage on the Altera site.,Hardware boards & demonstrations.,Many whitepaper and application notes on the website.,Core delivered with some whitepapers + FAQs.,9,Memory solutions Centre,DDR,DDR2,RLDRAM,QDR,User Guide,Whitepapers,Application Notes,Hardware test results,+,Reference designs,IBIS & SPICE models (I/O),Development Kits,Presentations,Articles,What is at the site?,What hardware exists?,High-Speed,Development Kit,Stratix,II,Edition,for DDR2 SDRAM,Stratix Memory Reference Platform I,for DDR SDRAM & RLDRAM II,Stratix II Memory Reference Platform II,for DDR2 SDRAM & QDRII SRAM,Stratix Memory Reference Platform II,for QDRII SRAM,12,Guidelines for Designing High-Speed FPGA PCBs,High-Speed Board Layout Guidelines Chapter,Altera Signal Integrity Center,Board Design Guideline Solution Center,Board Design Guideline References,+ Can Utilize Existing Board Design Files (Schematics, Gerber) etc,More on Board Guidelines,(Information given in this section is for guidance only. To predict best termination arrangements and board layout; simulate your design including PCB and device package.),14,Board Considerations,Micron has a lot of very useful materials,For example,Termination for Point-to-Point System (TN-46-06),Decoupling Capacitor Calculation for a DDR memory channel (TN-46-02),DDR33 Memory Design Guide for Two-DIMM Unbuffered Systems (TN-46-07) etc etc,Please download and use these, they contain a lot more detail than is here.,15,General Board Guidelines,Controlled impedance on signal layers:,All signal planes to be 50-ohms single ended impedance +/- 10%,All signal planes to be 100-ohms differential impedance +/- 10%,Component placement:,BGA to Surface-mount must have minimum 150-mil clearance.,Through-hole to Surface-mount on bottom side clearance must be greater than 200-mils,.,Via pads,Removed unused pad as these can cause additional unwanted capacitance.,16,General Board Decoupling,Use 0.1-F capacitors in an 0402/0603-sized package,Provide sufficient capacitance without adding too much inductance,Make VTT voltage decoupling on board close to the parallel pull-up resistors.,Connect the decoupling capacitors between VTT and ground.,Example,The Cyclone memory interface board has a 0.1-F capacitor for every other VTT pin.,The Cyclone memory interface board also has 0.1- and 0.01- F capacitors for every VDD and VDDQ pin.,17,Memory Board Power Routing,Example from S2MB2 :,GND, 3.3V, and 1.2V are routed as planes,These signals are needed across the board,VCCIO for the memories routed in a single split plane with 20-mil gaps of separation,Can use just part of the board for each memory,VTT and QDR VCCINT are routed as islands or 250-mil power traces on signal layers,Not needed for anything else except termination (for VTT),Oscillators and PLL power are routed as islands or 100-mil power traces on signal layers,Again, not needed for anything else,18,General Routing Guidelines,Altera recommends that designers:,Use 45 degree angles (no 90 degree corners),Avoid T-junctions for critical nets or clocks.,Avoid T-junctions greater than 250 mils,Disallow signals across split planes,Restrict routing other signals close to system reset signals,Avoid routing memory signals closer than 0.025 inch to PCI or system clocks,19,Routing Guidelines,Clock Routing Guidelines,Clocks should be routed on inner layers with outer-layer run lengths being held to under 500 mils,These signals should maintain a 10-mil spacing from other nets,Differential clocks should maintain a length-matching between P and N signals of +/- 15 mils, routed in parallel,Differential clocks with SMAs should route as a differential pair and break-out to SMAs right at the connectors,Space between pairs should be at least 3x that used between the pair,Must be routed differentially (5 mil trace, 10-15 mil space on centers) and be equal to or up to 100-mils longer than signals in the Address/Command Group,20,Routing Guidelines,Feedback Clock Routing Guidelines,Should be within 100-mils of the average length of the Byte Lane Groups,Address and Command Routing Guidelines,Address/Command can be unbuffered or buffered on DIMM,Unbuffered are more susceptible to cross talk and are generally nosier than buffered,Unbuffered should be routed on a different layer than DQ and DM and with greater spacing,21,Routing Guidelines,All Other Routing Guidelines,All data, address, and command signals must have matched length traces +/- 0.250 inches,All signals within a given “Byte Lane Group” should be matched length with maximum deviation of +/- 0.050 inches.,All other signals are to maintain a spacing that is based on its parallelism with other nets:,5 mils for parallel runs 0.5 inches (1X spacing relative to plane distance),10 mils for parallel runs between 0.5 and 1.0 inches (2X spacing relative to plane distance),15 mils for parallel runs between 1.0 and 6.0 inches (3X spacing relative to plane distance),22,Termination for Memories,The popular memories vendors do not require customers adhere strictly to the JEDEC specification for termination,Memory vendors do provide some suggested termination schemes and resistance values. Please reference these.,23,Termination for Memories,Termination ultimately need to be chosen by user for their particular board.,The following are some useful guidelines depending on the final scheme chosen,When pull-ups are used, fly-by termination configuration are recommended,Fly-by helps reduce stub reflection issues,Disadvantage is complexity of routing and cost,If using resistor networks,Do not share R-pack series resistors between address/command and data lines (DQ, DQS, DM) to eliminate crosstalk within pack,Series and pull up tolerances 1 2 %,If termination resistor packs used,Distance to your memory device 750 mils,Distance from your Stratix device 1250 mils,24,Board Guidelines,Do not forget to reference the schematics and gerber files that already exist for the Altera Memory boards.,25,A look at Frequency,26,Operational Frequency,Below 100 MHz device that support this ,Cyclone:,CycloneII:,Stratix: Recommend use on non-dqs mode.,StratixII: Recommend use on non-dqs mode.,Between 101 and 199 MHz,Cyclone:Up to 133 MHz operation,CycloneII: Up to 166 MHz operation,Stratix: Up to 200 MHz in DQS mode. 150 MHz in non-dqs mode.,StratixII: Up to 266 MHz in DQS mode. 150 MHz in non-dqs mode.,Above 200 MHz,StratixII: DDRII operation. Use of Fed-back clock recommended,27,Package has an effect.,Taken from AN348,Taken from AN342,28,Trying to run below 100 MHz,Generally DDR SDRAM devices do not run below 80 MHz.,Stratix DLL functions down to 100 MHz,For Stratix can use the Non-DQS mode. That is, a free running capture clock, it is often simpler.,Un-check this box for non-dqs mode,Running above 200 MHz,DDR only speced to 200 MHz (ie DDR400) so anything above is DDRII operation.,Timing is now critical,(although always important at any frequency),Fed back clock introduced,To compensate for PVT variations in output buffer and track length.,30,Fitting a controller or controllers,into a device,31,Pin Selection,DQ/DQS pins are fixed on the FPGA removing many of the difficult “best placement” choices.,Left with following pin selection choices,Memory Clocks,Use matched DDIO flops to create clocks?,Use dedicated PLL output for clocking?,DQ/DQS Groups,Which groups should a user choose?,32,Pin Selection Memory Clocks,Altera recommends using general purpose DDIO rather than dedicated pll output clock,Advantages,Using DDIO mimics the way DQS/DQ are generated (all PVT variations are tracked),Altera has the most system test data for this implementation,Prevent an issue in meeting the Tdqss requirement of the DDR specification. (That is, relationship between dqs and clock),33,Pin Selection - DQ/DQS Groups,Large interfaces (e.g. x72) use up most or all of the DQ/DQS groups on the top or bottom of the FPGA,Smaller interfaces present a choice to the user of which groups are best to use,Are any groups better matched on the FPGA?,Do any sets of groups provide better immunity to noise?,34,How wide an interface,Stratix:,DQS mode: Stratix devices have up to up to 160 dq pins. 80 on top and 80 on bottom (check specific package),Non-dqs mode any pin can be used but limited to 150 MHz operation.,StratixII:,DQS mode: Smaller packages have a low number of dqs pins so if interfacing to a DIMM check number of x8 dqs groups first.,Non-dqs mode: As above.,Cyclone:,8 global clocks in a cyclone. 2 of which are used up in the Altera DDR SDRAM IP controller. This leaves a total of 6 global clocks. DQS routed on global clock lines. Therefore maximum data width for a cyclone is 48 bits. (6 * 8 = 48) despite fact larger packages have 8 dqs pins.,35,Number of controllers in device,Applicable to Stratix/GX + StratixII,DQS mode,There are 2 DLL per device.,1 DLL can support N interface if,Enough pins,All interfaces running at same freqency,Startix only: The DLL on top (or bottom) can only feed dqs on its side.,Non-DQS mode,Can place controller in top/bottom or side banks.,However, this means operations limited to 150 MHz.,36,Number of controllers - limitation,Cant have 3 or more independent interfaces each running above 150 MHz,One interface would need to be below 150 and sit in side banks or,Two interface would need to be at same speed sharing 1 dll.,Example,4 interfaces running at, DDR266, DDR400, DDR333 and DDR333,The DDR266 (133MHz could go in the side banks).,The DDR400 could go in the top using 1 dll,The two DDR333 interface could sit in the bottom sharing the same DLL,37,Other,38,Cas Latency,Cas latency:,DDR 2.0 2.5 3.0,DDRII 3, 4, 5,Burst lengths,DDR: 2, 4, 8 DDR side (1, 2, 3, 4 local side),Restricted to 2 for Avalon (SOPC builder),DDRII: 4 (DDR side),39,Hardcopy,The timing scripts are designed and targeted at FPGA.,This means the core does not support Hardcopy,However, this does *NOT* mean that hardcopy doesnt support the core,It means that separate timing analysis for Hardcopy will need conducting.,40,The End,41,
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