BGA封装1

,Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,*,Electroplating Solder Bumping Flip Chip Technology,电镀焊球凸点倒装焊技术,Electroplating Solder Bumping Process,电镀焊球凸点工艺,Process Flow of Electroplating Solder Bump,电镀焊球凸点工艺流程,Chip,PR opening,Chip,Electroplated solder bump,Mushrooming,2.,Sputter Under Bump Metal,金属层溅射,3.,Coat with PR,覆盖光胶,4.,Pattern for bump,凸点光刻,5.,Electroplating,Cu and Sn/,Pb,焊料电镀,6.,Remove Resist,去除光胶,1.,Wafer with Al pad,钝化和金属化晶片,Chip,Passivation,Al contact pad,Chip,UBM,Chip,Thick photoresist film,Chip,7.,Strip Under Bump Metal,去除,UBM,Chip,8.,Reflow,回流,Chip,solder ball after reflow,Electroplating Solder Bumping,Process,电镀凸点制备工艺,Peripheral array solder bumps,周边分布凸点,Area array solder bumps,面分布凸点,The peak temperature of reflow process,回,流焊峰值温度：,220,C.,The effective bump pitch for peripheral array,周边分布有效凸点间距：,125,m.,Process Specification,工艺参数,Photoresist Thickness,光刻胶厚度:,40100,m,Bump Material,凸点材料:,63,Sn/37Pb,Bump height,凸点高度:,75140 ,m,UBM layer,凸点下金属层:,Ti,/W-Cu,Cr,-Cu,Min. effective pitch of bump,最小有效凸点间距,: 125 ,m,I/O array,输入/输出分布,:,peripheral array,周边分布,and area array,面分布,Flip Chip on Low-Cost Substrate Samples,Samples with Different Dimensions PCB,上不同尺寸倒装焊样品,Flip Chip on Flexible substrate,在软质底板上倒装焊,Direct chip attach on low-cost PCB, flexible substrate,已完成在低成本,PCB,和,软质底板上倒装焊工艺的研究,MCM-L technology,多芯片组装技术.,Stencil Printing Bumping Flip Chip Technology,丝网印刷凸点倒装焊技术,Electroless,UBM and Stencil Printing,化学镀,UBM,和丝网印刷工艺,The most potential,low cost,flip chip bumping method.,最具前景的低成本倒装焊凸点制备方法,Using,electroless,Ni/Au as UBM system,用化学镀镍/金作为凸点下金属层,maskless,process,无掩膜工艺,Compatible with SMT process,与表面贴装工艺兼容,Flexible for different solder alloys,适用于不同焊料合金,Chip,Solder Bump,Electroless Ni/Au,Passivation,Stencil Printing Process Flow,丝网印刷工艺流程,Process flow of Stencil Printing Process,丝网印刷工艺流程,(,not to scale,),Wafer preparation,晶片制备,(,Passivation and Al pads),Zincation Pretreatment,锌化预处理,Electroless Ni/Immersion Au,化学镀镍/金,Stencil Printing,丝网印刷,Solder Reflow and Cleaning,焊料回流和清洗,Stencil Printing Process Flow,丝网印刷工艺流程,Sketch of process flow,Electroless Ni/Au Stud (Cross section),化学镀镍/金,Solder Paste Printing,浆料印刷,Reflow,回流,Process Specification,工艺参数,I/O pads with a pitch of 400,m are used for testing dice,The limitation of this process is the pitch of 150,m.,测试芯片,I/O,凸点间距：400微米,Thickness of Ni/Au UBM is 56,m.,Ni/Au UBM,厚度,：56,微米,Different solder alloys are available.,Solder alloys from different vender:,Kester,Multicore, Alpha Metal, Indium,Different composition: eutectic,Pb,-,Sn,lead free,可应用不同供应商凸点焊料,Samples by Stencil Printing Bumping,丝网印刷凸点工艺样品,Flip Chip on PCB for Testing,在,PCB,上倒装焊测试样品,Reliability Test,可靠性测试,Reliability Test Design,可靠性测试设计,JEDEC Standard for Test Design,JEDEC,标准测试设计,(,Joint,Electron Device Engineering Council),Test Dice,测试芯片,Reliability Test (Thermal Cycling),可靠性测试,Mechanical Properties Test (Bump shear),机械测试,Low cost substrate,低成本底板,Bumping,凸点制备,Assembly (Bonding and Underfilling),装配工艺,Reliability Test Results,可靠性测试结果,Both Bumping Process Produce Reliable samples,两种凸点工艺样品的可靠性,Thermal Cycling,Temperature & Humidity,High temperature Storage,Multiple Reflows,No failure after 1500 cycles,No degradation after 1000 hours,No degradation after 10 reflows,Stencil Printing,Flip Chip,Electroplating,Flip Chip,Pass 1000 cycles,-40,C+125,C,1cycle/hr,JESD22-A104-B,No degradation after 100 hours,120,C and 85%RH,No degradation after 1000 hours,150,C, Air,JESD22-A103-A,Normal Reflow Profile,Results,Condition,Standard,Wafer Level Input/Output Redistribution,晶片级输入/输出再分布,Wafer Level Input/Output Redistribution Applications,晶片级,I/O,再分布技术的应用,Convert chips designed for perimeter,wirebond,to area flip chip bonding.,可转换已设计芯片，由周边丝键合至面分布倒装焊键合,Increase I/O density while increase I/O pitch.,增加,I/O,密度同时增加,I/O,间距,Improve reliability and manufacturing yield.,改善可靠性和制造率,Adapt existing chips designed for,wirebonding,to flip chip.,在现有已设计的丝键合芯片上应用倒装焊技术,Advantages,优点,WL-Input/Output redistribution will eliminate the,underfilling,process in Flip Chip Technology!,再分布技术可消除倒装焊技术中填充塑封工艺!,Redistribute tight pitch perimeter I/O to loose pitch array bonding and increase package reliability,增加焊点间距和封装可靠性,Peripheral,Area Array,Structure of I/O Redistribution,再分布结构,5,m,UBM (Ni),5,m,BCB_2,0.5,m,/5,m,Metal_2,(Ti-W/Cu),5,m,BCB_1,Key Feature :,Silicon substrate,BCB2,Metal 2,UBM,Al pad,120,m,80,m,100,m,120,m,250,m,300,m,Passivation,Solder ball,BCB1,Critical Dimension :,500,m,Solder ball pitch,300,m,Solder ball size (diameter),Process Flow of Redistribution Test Chip,再分布测试芯片工艺流程,Wafer start,Metal1,Al Sputtering,Photolithography,Wet etch,Passivation,PE-CVD SiO,2,Photolithography,Plasma dry etch,BCB 1,Spin coating,Photolithography,Hard Cure,Metal 2,Al sputtering,Photolithography,Wet etch,BCB 2,Spin coating,Photolithography,Hard Cure,Metal 2,Ti-W/Cu seed sputtering,Photolithography,Copper electroplating,Ti-W/Cu seed remove,Stencil solder printing,or,Solder Electroplating,or,Some of Flip Chip Equipment,倒装焊设备,Electroplating Station,电镀台,Wafer Stencil Printer,晶片丝网印刷机,Flip Chip Bonder,倒装焊机,Possible Business Relationship,合作方式,License of the technology,技术许可证,Joint venture with HKUST injecting the technology,合资：香港科大注入技术,Contract research - pre-defined deliverable for an agreed amount of $.,合作研究,Other schemes,开展其它合作模式,For more information contact,联系人,Prof. Philip Chan,陈正豪教授,(852) 2358-7041,Email:,eepchan,ust,.,hk,