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,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,单击此处编辑母版标题样式,MIPI,Protocol I,ntroduction,MIPI Development Team,2010-9-2,What is MIPI?,MIPI stands for,M,obile,I,ndustry,P,rocessor,I,nterface,MIPI Alliance is a collaboration of mobile industry leaders.,Objective to promote open standards for interfaces to mobile,application processors.,Intends to speed deployment of new services to mobile users by,establishing Spec.,Board Members in MIPI Alliance,Intel, Motorola, Nokia, NXP,Samsung, ST, TI,What is MIPI?,MIPI Alliance Specification for display,DCS (,D,isplay,C,ommand,S,et),DCS,is a standardized command set intended for command mode display modules.,DBI, DPI (,D,isplay,B,us,I,nterface,D,isplay,P,ixel,I,nterface),DBI,：,Parallel interfaces to display modules having display controllers and frame buffers.,DPI,：,Parallel interfaces to display modules without on-panel display controller or frame buffer.,DSI, CSI (,D,isplay,S,erial,I,nterface,C,amera,S,erial,I,nterface),DSI,specifies a high-speed serial interface between a host processor and,display module,.,CSI,specifies a high-speed serial interface between a host processor and,camera module,.,D-PHY,D-PHY,provides the,physical layer,definition for DSI and CSI.,DSI Layers,DCS spec,DSI spec,D-PHY spec,Outline,D-PHY,Introduction,Lane Module, State and Line levels,Operating Modes,Escape Mode,System Power States,Electrical Characteristics,Summary,Introduction for D-PHY,D-PHY describes a,source synchronous,high speed,low power, low cost,PHY,A PHY configuration contains,A Clock Lane,One or more Data Lanes,Three main lane types,Unidirectional Clock Lane,Unidirectional Data Lane,Bi-directional Data Lane,Transmission Mode,Low-Power signaling mode for control purpose,：,10MHz,(max),High-Speed signaling mode for fast-data traffic,：,80Mbps 1Gbps per Lane,D-PHY low-level protocol specifies a minimum data unit of,one byte,A transmitter shall send data,LSB first,MSB last,.,D-PHY suited for,mobile applications,DSI,：,Display Serial Interface,A clock lane, One to four data lanes.,CSI,：,Camera Serial Interface,Two Data Lane PHY Configuration,Lane Module,PHY consists of D-PHY (Lane Module),D-PHY may contain,Low-Power Transmitter,(LP-TX),Low-Power Receiver,(LP-RX),High-Speed Transmitter,(HS-TX),High-Speed Receiver,(HS-RX),Low-Power Contention Detector,(LP-CD),Three main lane types,Unidirectional Clock Lane,Master,：,HS-TX, LP-TX,Slave,：,HS-RX, LP-RX,Unidirectional Data Lane,Master,：,HS-TX, LP-TX,Slave,：,HS-RX, LP-RX,Bi-directional Data Lane,Master, Slave,：,HS-TX, HS-RX,LP-TX, LP-RX, LP-CD,Universal Lane Module Architecture,Lane States and Line Levels,The two LP-TXs drive the two Lines of a Lane,independently,and,single-ended,.,Four possible Low-Power Lane states,(LP-00, LP-01, LP-10, LP-11),A HS-TX drives the Lane,differentially,.,Two possible High Speed Lane states,(HS-0, HS-1),During HS transmission the LP Receivers observe,LP-00,on the Lines,Line Levels (typical),LP,：,01.2V,HS,：,100300mV,(Swing,：,200mV),Lane States,LP-00, LP-01, LP-10, LP-11,HS-0, HS-1,Operating Modes,There are three operating modes in Data Lane,Escape mode, High-Speed (Burst) mode and Control mode,Possible events starting from the Stop State of control mode,Escape mode,request (LP-11LP-10LP-00LP-01LP-00),High-Speed mode,request (LP-11LP-01LP-00),Turnaround,request (LP-11LP-10LP-00LP-10LP-00),Escape Mode,Escape mode is a special operation for,Data Lanes,using,LP,states.,With this mode some,additional functionality,becomes available,：,LPDT, ULPS, Trigger,A Data Lane shall enter Escape mode via,LP-11,LP-10,LP-00,LP-01,LP-00,Once Escape mode is entered, the transmitter shall send an,8-bit entry command,to,indicate the requested action.,Escape mode uses,Spaced-One-Hot Encoding,.,means each Mark State is interleaved with a,Space State (LP-00),.,Send Mark-0/1 followed by a Space to transmit a zero-bit/ one-bit,A Data Lane shall exit Escape mode via,LP-10,LP-11,Ultra-Low Power State,During this state, the Lines are in the,Space state (LP-00),Exited by means of a,Mark-1 state,with a length,TWAKEUP,(1ms) followed by a Stop state.,Escape Mode,Clock Lane Ultra-Low Power State,A Clock Lane shall enter ULPS via,LP-11LP-10LP-00,exited by means of a Mark-1 with a length,TWAKEUP,followed by a Stop State,LP-10 TWAKEUP LP-11,The minimum value of TWAKEUP is,1ms,High-Speed Data Transmission,The action of sending high-speed serial data is called,HS transmission,or,burst,.,Start-of-Transmission,LP-11LP-01LP-00SoT,(0001_1101),HS Data Transmission Burst,All Lanes will start synchronously,But may end at different times,The clock Lane shall be in High-Speed mode, providing a,DDR Clock,to the Slave side,End-of-Transmission,H Toggles differential state,immediately after last payload data bit,and keeps that state for a time,THS-TRAIL,High-Speed Clock Transmission,Switching the Clock Lane between Clock Transmission and LP Mode,A Clock Lane is a,unidirectional Lane,from Master to Slave,In HS mode, the clock Lane provides a,low-swing,differential DDR,clock signal.,the Clock Burst always,starts and ends with an HS-0 state,.,the Clock Burst always contains an,even number,of transitions,Summary for D-PHY,Lane Module, Lane State and Line Levels,Lane Module,：,LP-TX, LP-RX,HS-TX, HS-RX, LP-CD,Lane States,：,LP-00, LP-01, LP-10, LP-11,HS-0, HS-1,Line Levels (typical),：,LP,：,01.2V,HS,：,100300mV (Swing,：,200mV),Operating Modes,Escape Mode entry procedure,：,LP-11LP-10LP-00LP-01LP-00Entry Code LPD (10MHz),Escape Mode exit procedure,：,LP-10LP-11,High Speed Mode entry procedure,：,LP-11LP-01LP-00,SoT(00011101) HSD (80Mbps 1Gbps),High Speed Mode exit procedure,：,EoT,LP-11,Control Mode - BTA transmission procedure,：,LP-11LP-10LP-00LP-10LP-00,Control Mode - BTA receive procedure,：,LP-00LP-10LP-11,System Power States,Low-Power mode, High-Speed mode, Ultra-Low Power mode,Fault Detection,Contention Detection (LP-CD), Watchdog Timer, Sequence Error Detection (Error Report),Global Operation Timing Parameter,Clock Lane Timing, Data Lane Timing,Other Timing Initialization, BTA, Wake-Up from ULPS,Electrical Characteristics,HS-RX, LP-RX, LP-TX, LP-CD, Pin characteristic, Clock signal, Data-Clock timing,DC and AC characteristic,Outline,DSI,Introduction,Lane Distributor/Merger Conceptual,Packet Structure,Data Transmission Way,Processor-Sourced Packets,Peripheral-Sourced Packets,Reverse-Direction LP Transmission,Video Mode,Summary,Introduction for DSI,DSI is a Lane-scalable interface for increased performance.,One Clock Lane,/,One to Four Data Lanes,DSI-compliant peripherals support either of two basic modes of operation,Command Mode,(Similar to MPU IF),Data Lane 0,：,bidirectional,For returning data, ACK or error report to host,Additional Data Lanes,：,unidirectional.,Video Mode,(Similar to RGB IF),Data Lane 0,：,bidirectional or unidirectional;,Additional Data Lanes,：,unidirectional.,Video data should only be transmitted using HS mode.,Transmission Mode,High-Speed signaling mode,Low-Power signaling mode,Forward/Reverse direction LP transmissions shall use,Data Lane 0,only,For,returning data, DSI-compliant systems shall only use,Data Lane 0,in,LP Mode,Packet Types,Short Packet,：,4 bytes (fixed length),Long Packet,：,665541 bytes (variable length),Two Data Lanes HS Transmission Example,Data Transmission Way,Separate Transmissions,Separate Transmissions,KEY:,LPS Low Power State SP Short Packet,SoT Start of Transmission LgP Long Packet,EoT End of Transmission,Short Packet Structure,P,acket,H,eader,(4 bytes),Data Identifier (DI),* 1byte,：,Contains the Virtual Channel7:6 and Data Type5:0.,Packet Data,* 2byte,：,Length is fixed at two bytes,Error Correction Code,(ECC),* 1byte,：,allows single-bit errors to be corrected and 2-bit errors to be detected.,Packet Size,Fixed length 4 bytes,The first byte of any packet is the,DI (Data Identifier),byte.,DI7:6,：,These two bits identify the data as directed to one of four,virtual channels,.,DI5:0,：,These six bits specify the,Data Type,.,Long Packet Structure,P,acket,H,eader,(4 bytes),Data Identifier,(DI),* 1byte,：,Contains the Virtual Channel7:6 and Data Type5:0.,Word Count,(WC),* 2byte,：,defines the number of bytes in the Data Payload.,Error Correction Code,(ECC),* 1byte,：,allows single-bit errors to be corrected and 2-bit errors to be detected.,D,ata,P,ayload,(065535 bytes),Length = WC bytes,P,acket,F,ooter,(2 bytes),：,Checksum,If the payload has length 0, then the Checksum calculation results in,FFFFh,If the Checksum isnt calculated, the Checksum value is,0000h,Packet Size,4 + (065535) + 2 = 6 65541 bytes,Data Types for Processor-sourced Packets,Error Correction Code,P7 = 0,P6 = 0,P5 = D10D11D12D13D14D15D16D17D18D19D21D22D23,P4 = D4D5D6D7D8D9D16D17D18D19D20D22D23,P3 = D1D2D3D7D8D9D13D14D15D19D20D21D23,P2 = D0D2D3D5D6D9D11D12D15D18D20D21D22,P1 = D0D1D3D4D6D8D10D12D14D17D20D21D22D23,P0 = D0D1D2D4D5D7D10D11D13D16D20D21D22D23,Checksum,unsigned char xx = 0x01,0x5a,0x5a,0x03,0x08,0x2A, 0x00,0x01,0x00,0xF8,0x00,0xF6,0x57,0x00,0X00,0xE5;,typedef unsigned short U16;,typedef unsigned char U8;,U16 CRC_test;,U16 crc16_update(U16 crc, U8 a);,int main(),U16 crc,i;,crc = 0xFFFF;,for (i=0; i1; i+) crc = crc16_update(crc, xxi);,CRC_test = crc;,U16 crc16_update(U16 crc, U8 a),int i;,crc =a;,for (i = 0; i 1);,return crc;,Peripheral-to-Processor LP Transmissions,Detailed format description,Packet structure for,peripheral-to-processor,transactions is the same as for,the,processor-to-peripheral,direction,For a single-byte read response, valid data shall be returned in the,first byte,The second byte shall be sent as,00h,If the peripheral does not support Checksum it shall return,0000h,Peripheral-to-Processor LP Transmissions,Peripheral-to-processor transactions are of four basic types,Tearing Effect (TE),：,trigger message,(BAh),Acknowledge,：,trigger message,(84h),Acknowledge and Error Report,：,short packet (Data Type is 02h),Response to Read Request,：,short packet or long packet,Generic Read Response,、,DCS Read Response,（,1byte, 2byte, multi byte,）,Feature,BTA,shall take place after every peripheral-to-processor transaction,Multi-Lane systems shall use,Lane 0,for all peripheral-to-processor transmissions,Reverse-direction signaling shall only use,LP mode,of transmission,Video Mode,DSI supports three formats for Video Mode data transmission,Non-Burst Mode with Sync Pulses,Non-Burst Mode with Sync Events,Burst Mode,Summary for DSI,DSI is a Lane-scalable interface.,One Clock Lane,One to Four Data Lanes,Transmission Mode,High-Speed signaling mode (differential signal) (100mV300mV),Low-Power signaling mode (single-ended signal) (0V1.2V),For,returning data,only use,Data Lane 0,in,LP Mode,Packet Types,Short Packet,：,4 bytes (fixed length),Data ID,(1byte) +,Data0,(1byte) +,Data1,(1byte) +,ECC,(1byte),Long Packet,：,665541 bytes (variable length),Packet Header,(4 bytes) +,Data Payload,(065535 bytes) +,Packet Footer,(2 bytes),Operation Mode,Command Mode,(Similar to MPU IF),Video Mode,(Similar to RGB IF),Non-Burst Mode with Sync Pulses,Non-Burst Mode with Sync Events,Burst Mode,Thank you!,
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