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Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level, 2001 by Prentice Hall,Semiconductor Manufacturing Technology,by Michael Quirk and Julian Serda,Semiconductor Manufacturing Technology,Michael Quirk & Julian Serda,October 2001 by Prentice Hall,Chapter 11,Deposition,Objectives,After studying the material in this chapter, you will be able to:,1.Describe,multilayer metallization,. Discuss the acceptable characteristics of a thin film. State and explain the three stages of film growth.,2.Provide an overview of the different film deposition techniques.,3.List and discuss the 8 basic steps to a chemical vapor deposition (CVD) reaction, including the different types of chemical reactions.,4.Describe how CVD reactions are limited, reaction dynamics and the effect of dopant addition to CVD films.,5.Describe the different types of CVD deposition systems, how the equipment functions and the benefits/limitations of a particular tool for film applications.,6.Explain the importance of dielectric materials for chip technology, with applications.,7.Discuss,epitaxy,and three different,epi,-layer deposition methods,8.Explain spin on dielectrics.,Film Layers for an MSI Era NMOS Transistor,p,+,silicon substrate,p,-,epi,layer,Field oxide,n,+,n,+,p,+,p,+,n-well,ILD,Oxide,Pad,Oxide,Nitride,Topside,Gate oxide,Sidewall oxide,Pre-metal oxide,Poly,Metal,Poly,Metal,Figure 11.1,Process Flow in a Wafer Fab,Test/Sort,Implant,Diffusion,Etch,Polish,Photo,Completed wafer,Locations where thin,films are deposited,Unpatterned wafer,Wafer start,Thin Films,Wafer fabrication (front-end),Used with permission of Advanced Micro Devices,Figure 11.2,Introduction,Film Layering in Wafer Fab,Diffusion,Thin Films,Film Layering Terminology,Multilayer Metallization,Metal Layers,Dielectric Layers,Multilevel,Metallization,on a ULSI Wafer,Figure 11.3,Passivation,layer,Bonding pad metal,p,+,Silicon substrate,Via,ILD-2,ILD-3,ILD-4,ILD-5,M-1,M-2,M-3,M-4,p,-,Epitaxial layer,p,+,ILD-6,LI oxide,STI,n-well,p-well,ILD-1,Poly gate,n,+,p,+,p,+,n,+,n,+,LI metal,Metal Layers in a Chip,Micrograph,courtesy of Integrated Circuit Engineering,Photo 11.1,Film Deposition,Thin Film Characteristics,Good step coverage,Ability to fill high aspect ratio gaps (,conformality,),Good thickness uniformity,High purity and density,Controlled,stoichiometries,High degree of structural perfection with low film stress,Good electrical properties,Excellent adhesion to the substrate material and subsequent films,Solid Thin Film,Silicon substrate,Oxide,Width,Length,Thickness,Thin films are very thin in comparison to the substrate.,Figure 11.4,Film Coverage over Steps,Conformal step coverage,Nonconformal,step coverage,Uniform thickness,Figure 11.5,Aspect Ratio for Film Deposition,Aspect Ratio =,Depth,Width,=,2,1,Aspect Ratio =,500 ,250 ,500 ,D,250 ,W,Figure 11.6,High Aspect Ratio Gap,Photograph courtesy of Integrated Circuit Engineering,Photo 11.2,Stages of Film Growth,Continuous film,Gas molecules,Nucleation,Coalescence,Substrate,Figure 11.7,Techniques of Film Deposition,13,Table 11.1,Chemical Vapor Deposition,The Essential Aspects of CVD,1.Chemical action is involved, either through chemical reaction or by thermal decomposition (referred to as,pyrolysis,).,2.All material for the thin film is supplied by an external source.,3.The reactants in a CVD process must start out in the vapor phase (as a gas).,Chemical Vapor Deposition Tool,Photograph courtesy of,Novellus, Sequel CVD,Photo 11.3,CVD Chemical Processes,1.,Pyrolosis,: a compound dissociates (breaks bonds, or decomposes) with the application of heat, usually without oxygen.,2.,Photolysis,: a compound dissociates with the application of radiant energy that breaks bonds.,3.,Reduction,: a chemical reaction occurs by reacting a molecule with hydrogen.,4.,Oxidation,: a chemical reaction of an atom or molecule with oxygen.,5.,Reduction-oxidation (,redox,),: a combination of reactions 3 and 4 with the formation of two new compounds.,CVD Reaction,CVD Reaction Steps,Rate Limiting Step,CVD Gas Flow Dynamics,Pressure in CVD,Doping During CVD,PSG,BSG,FSG,Schematic of CVD Transport and Reaction Steps,CVD Reactor,Substrate,Continuous film,8)By-product removal,1) Mass transport of reactants,By-products,2) Film precursor reactions,3) Diffusion of gas molecules,4) Adsorption of precursors,5) Precursor diffusion into substrate,6) Surface reactions,7),Desorption,of byproducts,Exhaust,Gas delivery,Figure 11.8,Gas Flow in CVD,Gas flow,Deposited film,Silicon substrate,Reaction product,Diffusion of reactants,Figure 11.9,Gas Flow Dynamics at the Wafer Surface,Gas flow,Boundary layer,Gas flow,Stagnant layer,Figure 11.10,CVD Deposition Systems,CVD Equipment Design,CVD reactor heating,CVD reactor configuration,CVD reactor summary,Atmospheric Pressure CVD, APCVD,Low Pressure CVD, LPCVD,Plasma-Assisted CVD,Plasma-Enhanced CVD, PECVD,High-Density Plasma CVD, HDPCVD,CVD Reactor Types,Figure 11.11,Types of CVD Reactors and Principal Characteristics,Table 11.2,Continuous-Processing APCVD Reactors,Wafer,Film,Reactant gas 2,Reactant gas 1,Inert separator gas,(a) Gas-injection type,N,2,Reactant gases,Heater,N,2,N,2,N,2,N,2,N,2,Wafer,(b) Plenum type,Figure 11.12,Excellent Step Coverage of APCVD TEOS-O3,Figure 11.3,Planarized,Surface after,Reflow,of PSG,After,reflow,PSG,Before,reflow,PSG,Metal or polysilicon,Figure 11.14,Boundary Layer at Wafer Surface,Continuous gas flow,Deposited film,Silicon substrate,Boundary layer,Diffusion of reactants,Figure 11.15,LPCVD Reaction Chamber for Deposition of Oxides, Nitrides, or Polysilicon,Three-zone heating element,Spike thermocouples (external, control),Pressure gauge,Exhaust to,vacuum pump,Gas inlet,Profile thermocouples (internal),Figure 11.16,Oxide Deposition with TEOS LPCVD,Pressure controller,Three-zone heater,Heater,TEOS,N,2,O,2,Vacuum pump,Gas flow controller,LPCVD,Furnace,Temp. controller,Computer terminal operator interface,Furnace,microcontroller,Exhaust,Figure 11.17,Key Reasons for the Use of Doped Polysilicon in the Gate Structure,1.Ability to be doped to a specific,resistivity,.,2.Excellent interface characteristics with silicon dioxide.,3.Compatibility with subsequent high temperature processing.,4.Higher reliability than possible metal electrodes (e.g., aluminum),5.Ability to be deposited,conformally,over steep topography.,6.Allows for self-aligned gate process (see Chapter 12).,Doped Polysilicon as a Gate electrode,p,+,p,+,p,+,n,+,n,+,n,+,Figure 11.18,Advantages of Plasma Assisted CVD,1.Lower processing temperature (250 450C).,2.Excellent gap-fill for high aspect ratio gaps (with high-density plasma).,3.Good film adhesion to the wafer.,4.High deposition rates.,5.High film density due to low pinholes and voids.,6.Low film stress due to lower processing temperature.,Film Formation during Plasma-Based CVD,PECVD reactor,Continuous film,8)By-product removal,1) Reactants enter chamber,Substrate,2) Dissociation,of reactants by electric fields,3) Film precursors are formed,4) Adsorption of precursors,5) Precursor diffusion into substrate,6) Surface reactions,7),Desorption,of,by-products,Exhaust,Gas delivery,RF generator,By-products,Electrode,Electrode,RF field,Figure 11.19,General Schematic of PECVD for Deposition of Oxides, Nitrides, Silicon,Oxynitride,or Tungsten,Process gases,Gas flow controller,Pressure controller,Roughing,pump,Turbo,pump,Gas panel,RF generator,Matching network,Microcontroller,operator Interface,Exhaust,Gas dispersion screen,Electrodes,Figure 11.20,Properties of Silicon Nitride for LPCVD Versus PECVD,Table 11.3,High Density Plasma Deposition Chamber,Photograph courtesy of Applied Materials,Ultima,HDPCVD,Centura,Photo 11.4,Popular in mid-1990s,High density plasma,Highly directional due to wafer bias,Fills high aspect ratio gaps,Backside He cooling to relieve high thermal load,Simultaneously deposits and etches film to prevent bread-loaf and key-hole effects,Dep,-Etch-,Dep,Process,Film deposited with PECVD creates pinch-off at the entrance to a gap resulting in a void in the gap fill.,Key-hole defect,Bread-loaf effect,Metal,SiO,2,The solution begins here,1)Ion-induced deposition of film precursors,2)Argon ions sputter-etch excess film at gap entrance resulting in a beveled appearance in the film.,3)Etched material is,redeposited,. The process is repeated resulting in an equal “bottom-up” profile.,Cap,Figure 11.21,Five Steps of HDPCVD Process,1.Ion-induced deposition,2.Sputter etch,3.,Redeposition,4.Hot neutral CVD,5.Reflection,HDPCVD with Wafer at Throat of Turbo Pump,To roughing pump,Microwave 2.45,GHz,Electromagnet,Turbo,pump,Gate valve,Gas shower head,Wafer on electrostatic chuck,Figure 11.22,Dielectrics and Performance,Dielectric Constant,Gap Fill,Chip Performance,Low-k Dielectric,High-k Dielectric,Device Isolation,LOCOS,STI,3-Part Process for Dielectric Gap Fill,2)PECVD cap,Cap,1)HDPCVD gap fill,SiO,2,Aluminum,3)Chemical mechanical planarization,Figure 11.23,Potential Low-,k,Materials for ILD of ULSI Interconnects,Table 11.4,Interconnect Delay (RC) vs. Feature Size (,m),Figure 11.24,2.5,2.0,1.5,1.0,0.5,0,0.51.01.52.0,Feature size (,m,m),Delay time (,10,-9,sec),Interconnect delay (RC),Gate delay,Total Interconnect Wiring Capacitance,Capacitance (10,-12,Farads/cm),7,6,5,4,3,2,1,0,00.51.01.52.02.53.0,Space (,m,m),K = 4,K = 3,K = 2,K= 1,Redrawn with permission from Semiconductor International, September 1998,Figure 11.25,Low-,k,Dielectric Film Requirements,Table 11.5,General Diagram of DRAM Stacked Capacitors,SiO,2,dielectric,Doped polysilicon,capacitor plate,Doped polysilicon,capacitor plate,Buried contact,diffusion,SiO,2,dielectric,Doped polysilicon,capacitor plate,Doped polysilicon,capacitor plate,Buried contact,diffusion,Figure 11.26,Shallow Trench Isolation,Photograph courtesy of Integrated Circuit Engineering,Photo 11.5,Spin-on Dielectrics,Spin-on Glass (SOG),Spin-on Dielectric (SOD),Epitaxy,Epitaxy,growth methods,Vapor-phase,epitaxy,Metalorganic,CVD,Molecular-beam,epitaxy,Quality Measures,CVD Troubleshooting,Gap-Fill with Spin-On-Glass (SOG),2)SOG after curing,1)Initial SOG gap fill,3)CVD oxide cap,Cap,Figure 11.27,Proposed HSQ Low-,k,Dielectric Processing Parameters,Table 11.6,Epitaxy,Epitaxy,Growth Model,Epitaxy,Growth Methods,Vapor-Phase,Epitaxy,(VPE),Metalorganic,CVD (MOCVD),Molecular-Beam,Epitaxy,(MBE),Silicon Epitaxial Growth on a Silicon Wafer,Si,Si,Cl,Cl,H,H,Si,Si,Si,Si,Si,Si,Si,Si,Si,Si,Si,Cl,H,Cl,H,Chemical reaction,By-products,Deposited silicon,Epitaxial layer,Single silicon substrate,Figure 11.28,Illustration of Vapor Phase,Epitaxy,Dopant,(AsH,3,or,B,2,H,3,),H,2,SiH,2,Cl,2,RF induction-heating coils,Susceptor,Wafers,Vacuum,puimp,Figure 11.29,Silicon Vapor Phase,Epitaxy,Reactors,Exhaust,Exhaust,Exhaust,RF heating,RF heating,Gas inlet,Gas inlet,Horizontal reactor,Barrel reactor,Vertical reactor,Figure 11.30,Effects of Keyholes in ILD on Metal Step Coverage,b) SiO,2,is,planarized,c) Next layer of aluminum is deposited,Metal void caused by keyhole defect in SiO,2,a) SiO,2,deposited by PECVD,SiO,2,Keyhole defect in,interlayer dielectric,Aluminum,Figure 11.31,Chapter 11 Review,Deposition Quality Measures292,Troubleshooting292,Summary294,Key Terms295,Review Questions295,Equipment Suppliers Web Sites296,References296,
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