封装流程的介绍

TSTC RDE Organization Chaty,按一下以編輯母片文字樣式,第二層,第三層,第四層,第五層,IC,封 装 产 品 及 制 程 简 介,产 业 概 说,电子构装,(Electronic Packaging),，也常被称为封装,(Assembly),，是半导体产业中所谓的后段。它的目的在赋予集成电路组件组装的基础架构，使其能进一步与其载体,(,常是指印刷电路板）结合，以发挥原先设计的功能。,构装技术的范围涵盖极广，它应用了物理、化学、材料、机械、电机、微电子等各领域的知识，也使用金属、陶瓷、高分子化合物等各式各样的高科技材料。,在微电子产品功能与层次提升的追求中，开发构装技术的重要性不亚于,IC,制程中其它的微电子相关工程技术，故世界各主要电子工业国莫不戮力研究，以求得技术领先的地位。,Contents,1. IC,封装的目的,2. IC,封装的形式,3. IC,封装应用的材料,4. IC,封装的基本制程与质量管理重点,IC,封裝的目的,Why need to do IC packaging,防止湿气侵入,以机械方式支持导线,有效的将内部产生的热排出于外部,提供持取加工的形体,Whats,“ IC Package “,Package :,把包成一包,IC Package :,把 IC 包成一包,IC,封裝的形式,PIN,PTH IC,J-TYPE LEAD,SOJ、LCC,GULL-WING LEAD,SOP、QFP,BALL,BGA,BUMPING,F/C,Fundamental Lead Types of IC Package,IC Package Family,PTH IC：,DIP SIP、PDIP(CDIP),PGA,SMD IC:,SOIC, SOP(TSOP-I、TSOP-II)、SOJ,LCC, PLCC/CLCC,QFP, 1420/2828、,1010/1414(TQFP、MQFP、LQFP),Others, BGA、TCP、F/C,Something about IC Package Category,PTH IC,：,1960,年代发表，至今在一些低价的电子组件上仍被广泛应用。,DIP ,美商快捷首先发表,CDIP,。由于成本技术的低廉，很快成为当时主要的,封装形式；随后更衍生出,PDIP,、,SIP,等。,PGA ,美商,IBM,首先发表，仅应用于早期的高阶,IC,封装上，其,Grid Array,的,概念后来更进一步转换成为,BGA,的设计概念。,SMD IC : 1970,年代美商德州仪器首先发表,Flat Package,是所有表面黏着组件的滥觞。由于,SMD,有太多优于,PTH,的地方，各家厂商进一步发展出各具特色的封装。至今，表面黏着仍是先进电子组件封装设计的最佳选择。,QFP ,业界常见的形式以,1420/2828/1010/1414,四种尺寸为主。,LCC Chip carrier,，区分为,CLCC/PLCC,及,Leadless / Leaded,等形式。,SOIC Small Outline IC,；区分为,SOP(TSOP-I,、,TSOP-II),、,SOJ,两种主 流。,TCP Tape Carrier Package;,应用于,LCD Driver,。其锡铅凸块的设计后来进一步应用在,F/C,上。,当前最先进的封装技术：,BGA,、,F/C (,晶圆级封装）,IC Package application,Category of IC Package,Popular IC package types :,TSOP(,T,hin,S,mall,O,utline,P,ackage) QFP(,Q,uad,F,lat,P,ack),BGA(,B,all,G,rid,A,rray) CSP(,C,hip,S,cale,P,ackage),Category of IC Package-example 1,PBGA,QFP,TSOP,SOP,封裝應用的材料,Copper Lead frame,Epoxy Adhesive,Top Mold,Encapsulate Mold Compound,Die Paddle,Die,Bottom Mold,Gold Wire,TSOP,TSOP,Alloy42 Lead Frame,Ni42/Fe58,Tape,Die,Gold Wire,Encapsulate Mold Compound,Top Mold,Bottom Mold,TSOP Gross Section View,封裝原物料 金線 與 Compound,Ball Bond : Shape / Position,Height : 0.93 mil,Ball size : 3.04 mil,Ball aspect ratio : 0.30,Spec Criteria : 2.6 mil Ball size 5.2 mil,Gold Wire,與 Bonding Pad 的關係,After KOH etching view,Intermetallic,Gold Wire First Bond Section View,封裝原物料 Lead Frame 與 打線的關係,Conventional structure,Sectional View,IC chip,Inner Lead,wire,paddle,Signal,N/C,Signal,Signal,Power,Power,Power,Power,paddle,IC chip,Tie bar,Tie bar,Sectional View,Signal,Signal,Signal,Signal,Bus bar,Bus bar,wire,IC chip,Inner Lead,tape,IC chip,tape,Sectional View,Signal,Signal,Signal,Power,wire,IC chip,Inner Lead,IC chip,Signal,Power,Power,paddle,Wire Bonding 與 Lead Frame型態的演進,Multi-frame LOC structure,Tape LOC structure,Process Flow Chart, Equipment & Material,PROCESS,EQUIPMENT,MATERIAL,DIE SAW,DISCO 651,DIE ATTACH,HITACHI CM200( LOC),HITACHI LM400(LOC),WIRE BOND,SKW UTC-300,K&S 1488 / 8020/ 8028,1.0 MIL,MOLDING,TOWA Y- SERIES,SHINETSU KMC-260 NCA,MARKING,GPM / E & R LASER,Plating,MECO EPL-2400S,Sn / Pb 85/15,FORMING & SINGULATION,HAN-MI 203F,YAMADA CU-951-1,LEAD SCAN/FVI/PACK,RVSI LS3900DB / 5700,WAFER BACKGRINDRING,SIBUYAMA-508,SUNRISE,JEDEC 150 Deg C,FLOW,HITACHI CHIMICAL HM-122U,HAN-MI 101,DEJUNK,IC 封裝的基本製程 與 管制重點,Conventional IC Packaging Process Flow,IC封裝基本製造程序 : 以 TSOP - II Tape LOC 為例,1. Wafer Process,2. Die Attaching,3. Wire Bonding,4. Molding,5. Marking and Lead Process,TSOP Process Flow & Control,TSOP Process Flow & Control -Cont.,TSOP Process Flow & Control -Cont.,Our Reliability Test System,T/C , -55 C / 125 C , 5 cycles,Baking , 125 C , 24 hrs,Prepare Request Sheet,O/S Test, Visual/SAT Inspection,Moisture Soak Level I,85 C / 85%RH , 168hrs,Moisture Soak Level II,85 C / 60%RH , 168hrs,Moisture Soak Level III,30 C / 60%RH , 192hrs,IR Reflow , 220/235 C, 3X,O/S Test, Visual/SAT Inspection,PCT,TH,HAST,HTS,T/S,T/C,This flow / condition may be modified by customers request or special requirement,.,Pre - Condition,TCP & COF,Source: Samsungs web site,Driver IC,Slit,Driver IC,Solder mask,Resin,Gold bump,Adhesive,Driver IC,Base film,(PI),Resin,Gold bump,Driver IC,