TimeQuest使用教程

2007 Altera CorporationConfidential 2007 Altera CorporationTimingQuest使用教程使用教程 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationTimingQuestTimingQuest使用教程使用教程使用教程使用教程n简介n分析流程n时序分析中基本概念n使用TimeQuestnSDC Timing Constraintsn移植老的约束文件 2007 Altera CorporationConfidential 2007 Altera CorporationTimingQuest使用教程使用教程简介 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation TimingQuestTimingQuest时序分析器简介时序分析器简介时序分析器简介时序分析器简介n随着FPGA密度和速率的提高，传统FPGA时序分析工具很难满足复杂程度不同的设计需求。新的TimingQuest时序分析器可以达到基本和高级时序分析要求，提供完整的 GUI 环境，建立约束和时序报告，并提供 ASIC 功能特性，自然地支持业界标准的Synopsys设计约束(SDC)格式，以及全脚本功能。n与标准时序分析器(TAN)相比，TimeQuest(STA)都有明显的优势：基本时序分析要求-TimeQuest 提供使用方便的GUI，建立约束，查看时序报告。使用 TimeQuest可以提供和TAN相同的流程，不必再学习SDC或其他的约束格式。中间时序分析要求-TimeQuest 能够自然地支持SDC格式。TimeQuest简化了SDC学习过程，提供按需的交互式报告功能。高级时序要求-TimeQuest 提供全脚本功能，建立约束，生成报告，管理时序分析流程。TimeQuest支持高级报告，并且能够建立定制报告。2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationTimingQuestTimingQuest软件及器件支持软件及器件支持软件及器件支持软件及器件支持nQuartusII从6.0版本开始支持TimingQuest时序分析器nTimingQuest支持MAXII、Cyclone系列、Stratix系列和HardCopyII器件-在QII中选择以上器件时，可以选择使用TAN或STA分析-ArriaGX器件仅支持STA分析-Altera建议在90nm 和 65nm 工艺节点上所有新设计都使用TimingQuest-SDC是约束高速源同步接口(例如DDR和DDR2)和时钟复用设计结构的理想格式，对信号间复杂时序关系可以进行更高效的理解和精细的控制 Settings-Timing Analysis Settings下选择TAN或STA分析 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationTimingQuestTimingQuest支持支持支持支持Multi-CornerMulti-Corner分析分析分析分析nMulti-corner时序分析通过分析所有极端工作条件下(工艺，电压和温度)的设计来提高时序精度 n针对Stratix III和Cyclone III器件提供3-corner分析-在原先 Fast 0C和Slow 85C模型基础上添加了Slow 0C模型-针对65nm工艺器件甚至更高工艺器件提供完全的时序分析n在以性能为主的设计中，运行multi-corner分析是一种最终时序被认可(sign-off)的最好的方法-全编译期间，每个corner的时序报告会分别显示在编译报告中 2007 Altera CorporationConfidential 2007 Altera CorporationTimingQuest使用教程使用教程分析流程 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationCompilation FlowCompilation FlownTimeQuest is not the default timing analyzer-Can use TimeQuest for final timing sign-offn如果选择SDC时序约束，并不意味完全抛弃QSF的约束，只是忽略QSF文件中对时序方面的约束，毕竟QSF文件中还有I/O、逻辑等约束Analysis&SynthesisFitterClassic Timing AnalyzerTimeQuestSDCQSF 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationCompilation FlowCompilation FlownChoice of two static timing analyzer during compilation-Different timing constraint file requiredlTimeQuest(STA)=SDC filelClassic Timing Analyzer(TAN)=QSF filenTimeQuest can be used just as a static timing analysis tool-Requires an SDC file for timing analysis 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationCompilation with Compilation with TimeQuestTimeQuestnTimeQuest can be enabled for the entire compilation flow-Classic Timing Analyzer is disabledlQSF/Assignment Editor timing assignments are ignorednBoth TimeQuest and Fitter requires an SDC file 2007 Altera CorporationConfidential 2007 Altera CorporationTimingQuest使用教程使用教程时序分析中基本概念 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationHow does timing verification work?How does timing verification work?nTimeQuest与经典时序分析的模型都是一样的，区别在于TimeQuest会对异步时序也做出分析，下图中两条蓝色异步路径INCLKOUTDQCLRPREDQCLRPREcombinational delaysCLR 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation时序分析基本概念时序分析基本概念时序分析基本概念时序分析基本概念nLaunch vs.latch edgesnSetup&hold timesnData&clock arrival timenData required timenSetup&hold slack analysisnI/O analysisnRecovery&removalnTiming models 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationPath&Analysis TypesPath&Analysis TypesThree types of Paths:1.Clock Paths2.Data Path3.Asynchronous Paths*Clock PathsAsync PathData PathAsync PathDQCLRPREDQCLRPRETwo types of Analysis:1.Synchronous clock&data paths2.Asynchronous*clock&async paths*Asynchronous refers to signals feeding the asynchronous control ports of the registers 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation启动沿启动沿启动沿启动沿(Launch)(Launch)和锁存沿和锁存沿和锁存沿和锁存沿(Latch)(Latch)n启动沿启动沿(Launch)：寄存器至寄存器通路上，激活源寄存器的时钟沿n锁存沿锁存沿(Latch)：激活目的寄存器的时钟沿nREG1和REG2的时钟可以是同一个时钟源或不同时钟源产生n这些时钟源之间的关系可以确认寄存器到寄存器之间数据传输是否正常CLKLaunch Launch EdgeEdgeLatch Latch EdgeEdgeData ValidDATA 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationSetup&HoldSetup&HoldSetup:The minimum time data signal must be stableBEFORE clock edgeHold:The minimum time data signal must be stableAFTER clock edgeDQCLRPRECLKThValidDATATsuCLKDATATogether,the setup time and hold time form a Data Required Window,the time around a clock edge in which data must be stable.2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation数据到达时间数据到达时间数据到达时间数据到达时间(Data Arrival Time)(Data Arrival Time)n数据到达目的寄存器D输入引脚的时间n数据到达时间数据到达时间=启动沿启动沿(Launch)+Tclk1+Tco+Tdata nTclk1:源寄存器时钟路径的延迟 Tco:源寄存器从时钟输入引脚到数据输出引脚的网络延迟 Tdata:寄存器之间数据路径的延迟CLKREG1.CLKTclk1Data ValidREG2.DTdataLaunch EdgeData ValidREG1.QTcoREG1PRED QCLRREG2PRED QCLRComb.LogicTclk1TCOTdata 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation时钟到达时间时钟到达时间时钟到达时间时钟到达时间(Clock Arrival Time)(Clock Arrival Time)n时钟到达目的寄存器时钟输入引脚的时间n时钟到达时间时钟到达时间=锁存沿锁存沿(Launch)+Tclk2nTclk2:目的寄存器时钟路径的延迟n如果源寄存器和目的寄存器在同一时钟域上，那么锁存沿等于相对于启动沿的一个周期n如果在时钟不同的时钟域上，那么将采用启动沿与锁存沿实际的时间差CLKREG2.CLKTclk2Latch EdgeREG1PRED QCLRREG2PRED QCLRComb.LogicTclk2 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation数据要求时间数据要求时间数据要求时间数据要求时间 -建立建立建立建立(Data Required Time)(Data Required Time)n数据信号由源寄存器出发，必须到达目的寄存器输入的时间，以便被正确采样n数据到达时间数据到达时间=时钟到达时间时钟到达时间 TsunTsu时间取决于硬件CLKREG2.CLKTclk2Latch EdgeTsuData ValidREG2.DData must be valid hereREG1PRED QCLRREG2PRED QCLRComb.LogicTclk2Tsu 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation数据要求时间数据要求时间数据要求时间数据要求时间 -保持保持保持保持(Data Required Time)(Data Required Time)n数据到达目的寄存器最早的时间信号，不会影响前一时钟沿的数据采样n数据要求时间数据要求时间=时钟到达时间时钟到达时间+ThnTh时间取决于硬件CLKREG2.CLKTclk2Latch EdgeThData mustremain validto hereData ValidREG2.DREG1PRED QCLRREG2PRED QCLRComb.LogicTclk2Th 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation时序余量时序余量时序余量时序余量(Slack)(Slack)nSlack用于衡量时序是否满足设计的程度nSlack需要分别计算建立和保持SlacknSlack必须是正的，以确保正常工作n公式适用于所有时序通路-内部，I/O和异步控制建立建立Slack=建立需要的时间建立需要的时间 数据到达时间数据到达时间保持保持Slack=数据到达时间数据到达时间 保持需要时间保持需要时间 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationTclk2Setup Slack(建立建立Slack=建立需要的时间建立需要的时间 数据到达时间数据到达时间)REG2.CLKnThe margin by which the setup timing requirement is met.It ensures launched data arrives in time to meet the latching requirement.TsuCLKREG1.CLKTclk1Data ValidREG2.DTdataData ValidREG1.QTco Setup SlackLaunch EdgeLatch EdgeREG1PRED QCLRREG2PRED QCLRComb.LogicTclk1TCOTdataTclk2Tsu 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationHold Slack(保持保持Slack=数据到达时间数据到达时间 保持需要时间保持需要时间)REG2.CLKTclk2nThe margin by which the hold timing requirement is met.It ensures latch data is not corrupted by data from another launch edge.It also prevents“double-clocking”.ThCLKREG1.CLKTclk1Data ValidREG2.DTdataData ValidREG1.QTcoHoldSlackLatch EdgeNext Launch EdgeREG1PRED QCLRREG2PRED QCLRComb.LogicTclk1TCOTdataTclk2Th 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationFPGA/CPLD or ASSPASSP or FPGA/CPLDI/O AnalysisI/O AnalysisnAnalyzing I/O performance in a synchronous design uses the same slack equations-Must include external device&PCB timing parametersreg1PRED QCLRreg2PRED QCLRCL*TdataTclk1Tclk2TCOTsu/ThOSCData Arrival PathData Arrival PathData Required Path*Represents delay due to capacitive loading 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationRecovery&Removal(Recovery&Removal(恢复和消除恢复和消除恢复和消除恢复和消除)Recovery:The minimum time an asynchronous signal mustbe stable BEFORE clock edgeRemoval:The minimum time an asynchronous signal mustbe stable AFTER clock edgeDQCLRSETCLKTremValidASYNCTrecCLKASYNC 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationAsynchronous=Synchronous?Asynchronous=Synchronous?nAsynchronous control signal source is assumed synchronous-Slack equations still applyldata arrival path=asynchronous control pathlTsu Trec;Th Trem-External device&board timing parameters may be needed(Ex.1)n时序分析器是不会去分析真正的异步路径ASSPreg1PRED QCLRFPGA/CPLDreg2PRED QCLROSCFPGA/CPLDreg1PRED QCLRreg2PRED QCLRExample 1Example 2Data arrival pathData arrival pathData required pathData required path 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationTiming ModelsTiming ModelsnQII默认两种PVT(Process,Voltage,Temperature)条件下的时序模型-Slow Corner Model(最慢的性能)lIndicates slowest possible performance for any single pathlTiming at 85 C junction temp.and VCCMIN-Fast Corner Model(最快的性能)lIndicates fastest possible performance for any single pathlTiming at 0 C junction temp.and VCCMAXnWhy two corner timing models?-Ensure setup timing is met in slow model-Ensure hold timing is met in fast modellEssential for source synchronous interfacesnThird model(slow,0 C)available only for Stratix III and Cyclone III devices to support 65 nm and smaller technology(temperature inversion phenomenon)2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationTimeQuestTimeQuest网表基本单元网表基本单元网表基本单元网表基本单元nTimeQuest需要读入布局布线后的网表才能进行时序分析，读入的网表是由一系列的基本单元构成的，包括cell,port,pin等nTimeQuest分析器支持收集(Collections)API接口，可以直接访问设计中的网表基本单元。通过使用收集命令用来指定有效的时序约束，后面会详细介绍收集命令 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationTimeQuestTimeQuest网表基本单元网表基本单元网表基本单元网表基本单元nCells:Altera器件中的基本结构单元，LE可以看作是CellnPins:Cell的I/O端口，可以认为是LE的I/O端口-这里的Pins不包括器件的I/O引脚nNets:同一个Cell中，从输入Pin到输出Pin进过的逻辑-网表中连接两个相邻Cell的连线不被看作Net，被看作同一个点，等价于Cell的Pin-连接两个相邻Cell的连线还是具有其物理意义的，等价于Altera器件中的一段布线逻辑，会引入一定的延迟nPorts:顶层逻辑的I/O端口，对应已经分配的器件引脚nClocks:约束文件中指定的时钟类型的Pin，不仅指时钟输入引脚nKeepers:泛指Port和寄存器类型的CellnNodes:范围更大的一个概念，可能是上述几种类型的组合，还可能是不能穷尽的上述几种类型 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation收集收集收集收集(Collections)(Collections)nCollections are a group of objectsnTimeQuest supports the following collections:-all_clocks-all_inputs-all_outputs-all_registers-get_cells-get_clocks-get_keepers*-get_nets-get_nodes*-get_pins-get_ports-get_registers*SDC extensions 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationSimple SchematicSimple Schematic 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationTiming Timing NetlistNetlistnVery similar to the design implemented in the deviceTech Map ViewerTimeQuest Netlistdata_adata_bclk_aclk_bregaregband2reg3data_out 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationTiming Timing NetlistNetlistnCollectionsdata_adata_bclk_aclk_bregaregband2reg3data_outget_ports data_aDATAEDATAFDATACLKCLKDATADATACLKCOMBOUTCOMBOUTDATAINREGOUTREGOUTREGOUTPortsPinsCellsSample Pin Namesdata_a|COMBOUTrega|DATAINrega|CLKrega|REGOUTand2|COMBOUTand2|DATAESample Net Namesdata_bcomboutand2regaCOMBOUTCOMBOUTCOMBOUTget_cellsget_pinsregaregb|REGOUTLegend 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationName FinderName FindernEquivalent to the Node Finder in Quartus II-Only for TimeQuestnProvides an easy way to search for constraint and exception targets 2007 Altera CorporationConfidential 2007 Altera CorporationTimingQuest使用教程使用教程使用TimeQuest 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationUsing Using TimeQuestTimeQuest in in QuartusQuartus II Flow II FlowEnable TimeQuest in Quartus II projectSynthesize Quartus II projectUse TimeQuest to specify timing requirementsVerify timing in TimeQuestPerform full compilation(run Fitter)2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation进入进入进入进入TimeQuestTimeQuestnTools-TimeQuest Timing Analyzer，或点击按钮nTimeQuest图形化界面报告窗任务窗控制窗查看窗Menu access all TimeQuest features 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation任务窗任务窗任务窗任务窗n提供对常用操作的快速访问-命令执行-生成报告n按照默认设置执行大部分命令双击可执行任意命令 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation报告窗报告窗报告窗报告窗n显示目前可以看到的报告列表-报告由任务窗产生-使用报告命令生成报告，如在控制窗以tcl命令的方式输入点击对应的报告，在查看窗中了解详细信息 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation查看窗查看窗查看窗查看窗n主观察区显示报告表内容和图形结果-QII7.2对于查看窗进行了较大调整-路径显示比起TAN中的List Path功能更加详细直观，增加了波形显示-记住：Setup Slack=Data Required Time(Setup)Data Arrival Time Hold Slack=Data Arrival Time Data Required Time(Hold)-任一路径显示都可以实现Locate的功能，选中某一路径右键选择Locate Path或Locate Element-图中RF栏的定义l(empty):Unknown transitionlR:Rising outputlF:Falling outputlRR:Rising input,rising outputlRF:Rising input,falling outputlFR:Falling input,rising outputlFF:Falling input,falling output 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation控制窗控制窗控制窗控制窗n直接输入并执行SDC&Tcl命令-显示GUI执行的等价命令n显示TimeQuest输出消息n历史标签记录所有已经执行的SDC&Tcl命令 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation使用使用使用使用TimeQuestTimeQuest的步骤的步骤的步骤的步骤1.生成时序网表2.读取SDC文件(可选)3.约束设计(可选)4.更新时序网表5.生成时序报告6.保存时序约束(可选)n是否使用全部6个步骤取决于你所处的设计流程以及你打算如何使用工具n第2步与第3步二者必须选择一个 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation1)1)生成时序网表生成时序网表生成时序网表生成时序网表 Create Timing Create Timing NetlistNetlistn根据编译结果(post-map or post-fit)生成时序网表n三种方式来执行 1)create_timing_netlist的tcl命令2)Netlist菜单下Create Timing NetlistTcl等价命令3)任务窗双击第三种方式执行的是默认设置(Post-fit,Slow-corner)2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation2)2)读取读取读取读取SDCSDC文件文件文件文件(可选可选可选可选)Read SDC File)Read SDC Filen从SDC文件读取约束-如果没有SDC文件，可以跳过n执行-read_sdc的tcl命令lread_sdc n读取SDC文件(任务窗或者Constraints菜单下“Read SDC File”命令)n文件优先级(如果没有指定文件名)-专门加到QII工程中的文件(Settings中设置)-.sdc(如果存在)2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation3)3)约束设计约束设计约束设计约束设计(可选可选可选可选)Constrain design)Constrain designn直接加入新的约束-并没有实际加入到SDC文件中-可以使用GUI(Constraints菜单)或者控制窗输入tcl命令-如果所有约束都在SDC文件中，则不需要再添加约束n实例-create_clock-set_input_delay-set_output_delay 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation4)4)更新时序网表更新时序网表更新时序网表更新时序网表 Update Timing Update Timing NetlistNetlistn在当前的时序网表中应用SDC约束n会产生警告-未定义的时钟-部分定义的I/O延迟-组合循环n加入任何新的约束后，需要更新时序网表n执行-update_timing_netlist的tcl命令-Update Timing Netlist(任务窗或者Netlist菜单下)2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation5)5)生成时序报告生成时序报告生成时序报告生成时序报告n验证时序要求，找到违规(Violated)n检查全约束的设计，或者忽略时序约束n使用控制窗输入tcl命令、任务窗双击所需报告或者Reports菜单下 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation5)5)生成时序报告生成时序报告生成时序报告生成时序报告(续续续续)n任务窗中选择“Report Setup Summary”生成Setup报告发现有一条路径不满足约束(TNS=Total Negative Slack)n右键点击“Report Timing”生成相关路径的详细报告，直接点击“Report Timing”按钮，默认报告10条路径的信息n查看窗中显示10条路径的报告，分别点击各路径观察详细信息 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation“过时的过时的过时的过时的”报告报告报告报告 OUT OF DATE OUT OF DATEn再加入新的约束，会导致当前报告“过时”，背景以黄色高亮显示n更新时序网表，重新生成报告再次点击，即可重新生成报告 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation6)6)保存时序约束保存时序约束保存时序约束保存时序约束(可选可选可选可选)Write SDC File)Write SDC Filenwrite_sdc命令-将当前网表的所有约束保存到SDC文件中-如果已有SDC文件，可跳过此步骤。但如果再添加新约束，则需要使用此命令n注意-只有申请时，TimeQuest才生成SDC文件-运行report_sdc命令或执行Reports菜单下“Report SDC”命令，可以看到写入SDC文件的具体内容 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation其他命令其他命令其他命令其他命令nDelete Timing Netlist-从网表中清除所有应用的时序约束-输入delete_timing_netlist命令或执行Netlist菜单下“Delete Timing Netlist”nreport_clocks命令-报告所有定义的时钟nreport_clock_transfers命令-报告混合时钟域的路径nreport_ucp命令-报告未约束的路径nReset Design-迅速删除并重新生成当前时序网表-等价于先后执行delete_timing_netlist和create_timing_netlist命令-输入reset_design命令或执行Constraints菜单下”Reset Design”2007 Altera CorporationConfidential 2007 Altera CorporationTimingQuest使用教程使用教程SDC Timing Constraints 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationSDC Timing ConstraintsSDC Timing ConstraintsnClocksnI/OnAsynchronous pathsnLatchesnFalse pathsnMulticycle pathsnAbsolute delaysnTime Groups 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationClocks in SDCClocks in SDCnTwo types-ClocklAbsolute or base clock-Generated ClocklTiming derived from another clock in design-Must have defined relation with source clocklApply to output of logic function that modifies clock input-PLL输出,分频时钟(包括反相时钟),输出时钟,行波时钟等n默认情况下所有的时钟是相关的-所以TimeQuest会分析混合时钟域之间的路径 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationClock ConstraintsClock ConstraintsnCreate ClocknCreate Generated ClocknClock UncertaintynClock LatencynPLL clocks 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationCreate Clock using GUICreate Clock using GUIName Finder等效等效Tcl命令命令 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationCreate Generated Clock using GUICreate Generated Clock using GUI 2007 Altera CorporationConfidentialAltera,Arria,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera CorporationGenerated Clock Example 1create_clock period 10 get_ports clk_increate_generated_cl