IC测试简介

IC 測試工程簡介測試工程簡介ASE Test“The Fundamentals of Digital Semiconductor Testing”Ver:2.03 Sep.1999ISBN#0-9658797-0-4 Soft Test The BasicsScientific/Engineering NotationBasic Terms:The DUT:Device Under Test.Signal Pins:Input,Output,Tri-State&Bi-directional Pins.Power Pin:Vcc,Vdd,Vss.Vcc:The power pin that supplies voltage for a TTL device.Vdd:The power pin that supplies voltage for a CMOS device.Vss:To provide a return path for Vdd or Vcc pin.Ground:To connect a signal pin or other electrical node to the test system reference node or to Vss.On a device with only one power supply voltage,Vss is often called“ground”.Ohms LawMeasuring Resistance(I)Forcing Current&Measuring VoltageMeasuring Resistance(II)Forcing Voltage&Measuring Current DC TestingTopics1.Opens/Shorts Test2.Output Levels Test3.Input Levels Test4.Input Leakage Current Test5.IDD Current Test6.Tri-State Leakage Current Test7.Output Short Circuit Current Test8.Input Clamp Diode TestWhy Test for Opens and Shorts?1)Also called continuity or contact test.4)Quickly determine whether a device has shorted .pins,missing bond wires,a pin damaged from ESD1,a manufacturing defect,etc.2)Verify that during a device test,electrical contact .is made to all signal pins on the DUT and that no .signal pin is shorted to another signal pin or .power/ground.3)Verify test system related problems such as:.Probe card,Load board,Socket,etc.Opens/Shorts Test Serial/Static Method,VDD DiodeGround all pins(including VDD).Set voltage clamp 3.0VUsing PMU,force+100uA,one pin at a time.Measure resultant voltage.Fails test(open)if voltage measured is greater than+1.5V.Fails test(shorted)if voltage measured is less than+0.2V.PMU TestLimitsDUT+100 uA0.650 VForceMeasurePMUDUTSignalPinVDD=0VSS=0VFailOpenPASSFail ShortedGT+1.5VLT+0.2V100uAVOLTAGECURRENTVOLTAGECURRENTGround all pins(including VDD).Set voltage clamp-3.0VUsing PMU,force-100uA,one pin at a time.Measure resultant voltage.Fails test(shorted)if voltage measured is greater than-0.2V.Fails test(open)if voltage measured is less than-1.5V.PMU TestLimitsDUT-100 uA-0.650 VForceMeasurePMUDUTSignalPinVDD=0VSS=0VFailShortedPASSFail OpenGT-0.2VLT-1.5V-100uAVOLTAGECURRENTVOLTAGECURRENTOpens/Shorts Test Serial/Static Method,VSS DiodeDatalog of:Opens and Shorts using the PMUOpens and Shorts-Key Points Serial/Static MethodPurpose:To detect open or shorted device pins and verify proper connections between the test system and the DUT.Test one pin at a time,DC serial/static test methodForce current,measure voltageTest requirements not found in device specificationsThis test very time consuming(slow and costly)Opens and Shorts Test-Notes This test method is used to test signal pins(inputs&outputs)but not power pins such as Vdd or Vss.Power and ground pins may also be tested for an open condition,but their structure is different from that of a signal pin.Test the power pins,observe the measured value on a good device,and set the test limits accordingly.Opens/Shorts Test Functional Method,VDD DiodeGround all pins(including VDD).Program dynamic loads to+400uA at 3V.Set VOL/VOH Z-mode(fail/pass/fail)Run functional pattern(test one pin at a time)Test for diode voltage.Fails if voltage is greater than 1.5V.Fail if voltage is less than 0.2VFunctionalTest LimitsFailOpenPASSFail ShortedGT+1.5VLT+0.2VDUTDUTSignalPinVDD=0VSS=0V+400uAat+3V+400uA+3VF1F2+0.2V+1.5VVIHVILVector DataIOLIOHVREFVOHVOLHi TripLow TripA functional test pattern must be developed which will execute the following sequence:Sample Test Vector File for Opens/ShortsOpens/Shorts Test Functional Method TimingPin driver forces 0V in prior cycle.Pin driver turns off,current load turns on at start of period.Output strobe allows time for pin voltage to settle.If pin is good,output charges to 1 diode voltage(+0.65V).If pin is open,output charges to VREF(GT+1.5V).If pin is shorted,output stays low(LT+0.2V).PASSFAIL OPENFAIL SHORTED1uSecDriver onDUT Pin under testTester output strobeToToDriver off,current load onOutput strobe Window at 0.9uSecVOH=+1.5VVOL=+0.2V+0.65V0VOpens/Shorts Test Functional Method,VSS DiodeGround all pins(including VDD).Program dynamic loads to-400uA at-3V.Set VOL/VOH Z-mode(fail/pass/fail)Run functional pattern(test one pin at a time)Test for diode voltage.Fails if voltage is more than-0.2V.Fail if voltage is less than-1.5VDUTFunctionalTest LimitsFailShortedPASSFail OpenGT-0.2VLT-1.5VDUTSignalPinVDD=0VSS=0V-400uAat-3V-400uA-3VF1F2-1.5V-0.2VVIHVILVector DataIOLIOHVREFVOHVOLHi TripLow TripOpens and Shorts-Key Points Functional MethodPurpose:To detect open or shorted device pins and verify proper connections between the test system and the DUT.Functional test serial/dynamic test methodUses programmable current loads and functional comparatorsTest requirements not found in device specificationsMuch faster than the DC serial/static methodOutput Voltage Test-VOH/IOH Serial/Static MethodApply VDDmin.Set voltage clamp.Precondition output to logic 1(output high)Using PMU,force IOH current per specification.Wait 1 to 5 mSec(Set PMU delay).Measure resultant voltage.Fails VOH if measured voltage is less than+2.4V.PMU TestLimitsPASSFAIL VOHLT+2.4V-5.2mA4.3 VForceMeasurePMUVOLTAGECURRENTVOLTAGECURRENTDUTOutputPinIOHDUTVDDminVSS=0VONOFFOutput Voltage Test-VOL/IOL Serial/Static MethodApply VDDmin.Set voltage clamp.Precondition output to logic 0(output low)Using PMU,force IOL current per specification.Wait 1 to 5 mSec(Set PMU delay).Measure resultant voltage.Fails VOL if measured voltage is greater than+0.4V.PMU TestLimitsPASSFAIL VOLGT+0.4V8.0mA0.15 VForceMeasurePMUVOLTAGECURRENTVOLTAGECURRENTDUTOutputPinIOLDUTVDDminVSS=0VONOFFVOH/IOH-Key Points Serial/Static MethodPurpose:To verify the ability of an output to provide current(IOH)at a specified voltage(VOH).This test verifies the resistance of the output buffer.DC static test uses PMU to force current and measure voltageTest requires outputs to be preconditioned to logic 1Test limits defined in device specificationsVDDmin is worst case test conditionVOH/IOH Resistance CalculationDUTOutputPinIOHActual device Output circuitVDDminVSS=0VONOFFSpecificationIOH(min)=-5.2mAVOH(min)=2.4VVDD(min)=4.75VVSS=0VONOFFIOHEVOHE=VDD-VOHR=E/IE=4.75-2.4=2.35R=2.35/0.0052R=452 Ohms(max)Equivalent circuitfor Rout calculationVOL/IOL-Key Points Serial/Static MethodPurpose:To verify the ability of an output to sink current(IOL)without exceeding the specified voltage(VOH).This test verifies the resistance of the output buffer.DC static test uses PMU to force current and measure voltageTest requires outputs to be preconditioned to logic 0Test limits defined in device specificationsVDDmin is worst case test conditionFunctional VOL/VOH TestFunctionalTest LimitsPass LowFAILPass HighVDDminVSS=0VDUTOutputPinIOHDUTIOLVREFCurrent LoadIOLIOHVOHVOLHiLoComparatorsHi TripLo TripPin ElectronicsSet programmable loads to IOL/IOH spec for each output.Set comparator levels to VOL/VOH spec for each output.Execute functional test pattern which tests all outputs for logic 0 and logic 1 levels.Note:You may need to run pattern at a reduced test rate.VOL/VOH-Key Points Functional MethodPurpose:To verify that the output buffers will properly supply the correct amount of current(IOL/IOH)at the proper voltage(VOL/VOH).Dynamic functional test must be executed.Test limits defined in device specifications.Test requires current loads on output pins.It may not be possible to test all output pins simultaneously when fully loaded,due to noise produced by high currents.VIL/VIH Levels TestComparatorTest LevelsPASS Logic 1FAILVOH SpecPASS Logic 0VOLSpecApply VDDmax.Apply input levels as defined in specification.Relax all other parameters and execute functional test pattern.Monitor output signals during test.Fails test if any output level is different from expected.Repeat test at VDDmin.Pin ElectronicsPin ElectronicsDrivers Apply VIL/VIH Levels to All Inputs Comparators Test All Outputs for relaxed VOH/VOL LevelsVSS=0VDUTVDDVIL/VIH-Key PointsPurpose:To verify that the input buffers will properly detect VIL and VIH voltage levels.VIL/VIH can only be verified by executing a dynamic functional test.Test limits are defined in device specifications(often as DC).Output pins fail as a result of improper operation of input circuitry.Input Leakage Low Test-IIL Serial MethodPin Electronics force logic 1 on all inputsDUTIILDUTSignalPin0.0V-0.001nAForceMeasurePMUVOLTAGECURRENTVOLTAGECURRENTVDDmaxVSS=0VPMU Test LimitsPASSFAIL IILLT-10.0uAApply VDDmax.Precondition all inputs to logic 1 with pin drivers.Using PMU,force individual inputs to VSS.Wait 1 to 5 mSec(Set PMU delay).Measure resultant current.Fails IIL if measured current is less than-10.0uA.Input Leakage High Test-IIH Serial MethodPin Electronics force logic 0 on all inputsDUTIIHDUTSignalPin5.25V0.001nAForceMeasurePMUVOLTAGECURRENTVOLTAGECURRENTVDDmaxVSS=0VPMU Test LimitsPASSFAIL IIHGT+10.0uAApply VDDmax.Precondition all inputs to logic 0 with pin drivers.Using PMU,force individual inputs to VDDmax.Wait 1 to 5 mSec(Set PMU delay).Measure resultant current.Fails IIH if measured current is greater than+10.0uA.Input Leakage Test-IIL/IIH Ganged MethodApply VDDmax.Using PMU,force all input pins to VDDmax.(IIH)Wait 1 to 5 mSec(Set PMU delay).Measure resultant current.Fails IIH if measured current is outside limits.Repeat test forcing all input pins to VSS.(IIL)If test fails,retest using serial method.DUTIIHDUTSignalPin0.0V-0.001nAForceMeasurePMUVOLTAGECURRENTVOLTAGECURRENTVDDmaxVSS=0VIILSingle PMU connected to all inputsPMU Test LimitsPASSFAIL IIHGT+10.0uAFAIL IILLT-10.0uAInput Leakage Test-IIL/IIH Parallel MethodApply VDDmax.Using PMU per pin,force each pin to VDDmax.(IIH)Wait 1 to 5 mSec(Set PMU delay).Measure resultant current.Fails if measured current(per pin)is outside limits.Repeat test forcing each pin to VSS.(IIL)PMU Test LimitsPASSFAIL IIHGT+10.0uAFAIL IILLT-10.0uADUTIIHVDDmaxVSS=0VIILPMU per pin0.0V0.001nAForceMeasureVOLTAGECURRENTVOLTAGECURRENT0.0V0.001nAForceMeasureVOLTAGECURRENTVOLTAGECURRENT0.0V0.001nAForceMeasureVOLTAGECURRENTVOLTAGECURRENTDUTSignal PinDUTSignal PinDUTSignalPinIIL/IIH-Key Points Serial/Static MethodPurpose:To verify that the input buffers offer a high resistance when applying 0V and VDD.DC test uses PMU to force voltage and measure currentSerial test method is very slow-use alternative method if possibleTest limits defined in device specificationsVDDmax is worst case test conditionNo resistive path.Very high resistance.Low leakage currents.DUTInputPinLow leakage Input circuitVDDVSSPull-Down from input to VSS.Lower resistance value.Higher input leakage current.DUTInputPinPull-Down Input circuitVDDVSSPull-Up from input to VDD.Lower resistance value.Higher input leakage current.DUTInputPinPull-Up Input circuitVDDVSSCMOS Input Structures Resistive Input:Pull-Ups&Pull-DownsResistive Inputs-Key PointsPurpose:To verify that the input buffers were manufactured with the correct resistance paths to either VDD or Ground.Ganged testing will not work.Dual test limits are often used to test for a range of acceptable resistance.Why Test for Gross IDD Current?1)Quickly determine if it is reasonable to continue to test.2)Performed immediately after the opens/shorts test.3)Prevent test hardware from being damaged.Gross IDD TestUsing DPS or PMU,apply VDDmax.Set maximum current clamp on DPS/PMU.Set Pass/Fail limits.Set all inputs Low/High or execute reset sequence.Stop pattern.Wait 5 to 10mSec.Measure current flowing into VDD pin(s).Fails IDD if measured current is outside of limits.VSS=0VDUTVDDmax5.25V+8.7mAForceMeasurePMU or DPSVOLTAGECURRENTVOLTAGECURRENTIDDVector memory&Pin Electronics(Apply reset pattern)PMU Test LimitsPASSFAIL IDDLT-1.0mAFAIL IDDGTIDDLimitGross IDD-Key PointsPurpose:To detect high power supply currents upon initial power up.IDD test is often performed immediately after the opens/shorts test.(Very useful at wafer test).DC static test using PMU or DPS.Test requirements not found in device specifications.Limit is relaxed vs.IDD static and dynamic testsTest requires simple preconditioning patternDoes not require precise preconditioningStatic IDD TestUsing DPS or PMU,apply VDDmax.Execute preconditioning pattern.Stop pattern.Wait 1 to 5mSec(Set delay).Measure current flowing into VDD pin(s).Fails IDD test if measured current is greater than IDD spec.VSS=0VDUTVDDmax5.25V+19.2uAForceMeasurePMU or DPSVOLTAGECURRENTVOLTAGECURRENTIDDVector memory&Pin Electronics(Apply preconditioning pattern)PMU Test LimitsPASSFAIL IDDGTIDDSpec.Static IDD-Key PointsPurpose:To detect power supply currents when the device is preconditioned to its lowest current consumption mode.DC static test using PMU or DPS to supply VDD and measure current.Effective method of identifying processing problems within CMOS devices.Test limits defined in device specifications,but exact preconditioning may not be defined.Test requires preconditioning pattern.CMOS IDD currents are affected by input levels,input pull-up and pull-down resistors,VDD levels,vector sequence,output current loading and output capacitance loading.IDDQ Test The IDDQ test measures the quiescent current under varying logic conditions and provides improved test coverage as compared to the standard Static IDD test.To perform this test a sequence of Static IDD tests,consisting of 6 to 12 individual current measurements,is performed at unique points within the functional vector set.The intent of the test vector sequencing is to toggle on and off as many internal gates as possible while verifying the amount of IDD leakage current at each vector stopping point.The IDDQ test may detect minor defects within the core of the circuit that could not otherwise be detected.Dynamic IDD TestUsing DPS or PMU,apply VDDmax.Execute continuous pattern.Wait 5 to 10mSec(Set delay).Measure current flowing into VDD pin(s)while device is actively executing pattern.Fails IDD if measured current is greater than IDD spec.Stop the pattern.VSS=0VDUTVDDmax5.25V+12.4mAForceMeasurePMU or DPSVOLTAGECURRENTVOLTAGECURRENTIDDVector memory&Pin Electronics(Apply continuous pattern)PMU Test LimitsPASSFAIL IDDGTIDDSpec.Dynamic IDD-Key PointsPurpose:To detect power supply currents when the device is active.DC dynamic test using PMU or DPS to supply VDD and measure current.Test limits defined in device specifications,but exact preconditioning may not be defined.Test requires preconditioning pattern and pattern which executes during measurement.CMOS IDD currents are affected by input levels,VDD levels,output current(resistive and capacitive)loading,vector sequence,output capacitive loading and test frequency.Tristate Leakage Test-IOZ PMU MethodApply VDDmax.Precondition output to tristate.Using PMU,force VSS.Wait 1 to 5 mSec(Set PMU delay).Measure resultant current.Fails IOZ if measured current is less than-2uA.Repeat with PMU forcing VDDmax.Fails IOZ if measured current is greater than+2uA.PMU Test LimitsPASSFAIL IOZLT-2uAFAIL IOZGT+2uADUTI/OPinOutput BufferInput BufferInternal Device SignalInternal Device SignalI/OEnableLogic Diagram Internal Device SignalVDDmaxVSSOFFOFFVDDmaxVSSDUTI/OPinInternal Device SignalOutput BufferEquivalent Schematic Diagram Input BufferIOZ-Key Points PMU MethodPurpose:To verify that tri-state output buffers offer an extremely high resistance when in the off state.DC static test uses PMU to force voltage and measure current.Test limits defined in devices specifications.Test requires preconditioning.Performed only on three-state outputs and bi-directional pins.VDDmax is worst case test condition.Functional Z-State TestApply VDDmax.Enable tristate mode testing.Set comparator levels to VOL and VOH values.Execute tristate pattern.Note:Modifying(decreasing)the test rate may be required to allow the loads to pull the outputs to VREF.Fails IOZ if any output is outside comparator trip limits.Comparator Level LimitsPASSFAIL IOZLT+0.4VFAIL IOZGT+2.4VDUTI/OPinOutput BufferInput BufferInternal Device SignalInternal Device SignalI/OEnable2.0VVREFDynamic LoadIOLIOHVOHVOLHiLoComparatorsDUTPin ElectronicsFunctional Z-State-Key PointsPurpose:To insure that bi-directional and high impedance outputs are capable of achieving a high impedance or off state.Dynamic functional test must be executed.Test conditions are not defined in device specifications.Test requires loads on outputs to provide intermediate voltage.Test is affected by external capacitance on outputs.Output Short Circuit Current Test-IOSApply VDDmax.Precondition output to logic 1.Set current clamp.Using PMU,force 0.0V.Wait 1 to 5 mSec(Set PMU delay).Measure resultant current.Fails test if measured current is outside limits range.PMU Test LimitsPASSFAIL IOSLT-85mAFAIL IOSGT-30mAVDDmaxVSS=0VONOFFDUTOutputPinPMU0.0V-52.4mAForceMeasureVOLTAGECURRENTVOLTAGECURRENTIOSDUTIOS-Key PointsPurpose:To verify the integrity of the output during maximum current flow.DC static test uses PMU to force voltage and measure current.Test limits defined in devices specifications.Dual test limits are often used to test for a range of current.This test is performed on only one output pin at a time.Input Clamp Diode Test-VI 0VDUT-18.0mA-0.732VForceMeasurePMUVOLTAGECURRENTVOLTAGECURRENT-18mAPMU Test LimitsPASSFAIL VILT-1.5VTTLInputPinVCCminTest applies only to TTL type devices.Apply VCCmin.Set voltage clamp.Using PUM,force-18mA(input pins only).Measure resultant voltage.Fails test if measured voltage is less than-1.5V.VI-Key PointsPurpose:To verify the integrity of the input structure.Input Clamp(VI):VI represents the voltage(V)measured on the input(I)when a negative current is forced from the input of a TTL(not CMOS)devices.DC static test using PMU to force current and measure voltage.Test limits defined in devices specifications.Performed on TTL devices only.Performed on one pin at a time.Functional TestingTopics1.Pin Electronics(PE)Card 2.Input signal creation 3.Output signal creation4.Basic concept of functional testingVIHVILDUTVOHVOLIOLIOHVREFHigh Speed I/O SwitchF1F2Driver(Inputs)Current Load(Outputs)Voltage Receiver(Outputs)PMU ConnectionFormatted Vector DataVout ComparatorsForceSenseForceForceLogic 1Logic 0Iout ComparatorsI High compare+-+-I Low compareVREFHigh Speed Current Comparators0.0V0.001nAForceMeasureVOLTAGECURRENTVOLTAGECURRENTOptionalOptionalPMU per pinOptionalK1K2K3 Pin ElectronicsThe Pin Electronics The pin electronics(also called the Pin Card,PE,PEC or I/O card)is the interface between the test system resources and the DUT(Device Under Test).It will contain:Driver circuitry to supply input signals.I/O switching circuitry for turning drivers and current loads on and off.Voltage comparator circuitry for detecting output levels.A connection point to the PMU.Programmable current loads.Possibly additional circuitry for making high speed current measurements.Possibly a per pin PMU.Functional TestingFunctional Test Results PASS/FAILHi TripLow TripIOLIOHVREFVOHVOLVIHVILDriverDUTComparatorsCurrent LoadI/O SwitchInput Timing,Formats&I/O controlTime Set ControlOutput control&Strobe timingOutput StrobeTiming DataInput Timing&Format DataI/O ControlFormattedInput dataVector Data Input&OutputTiming&Formatting ControlPin Electronics(PE)CardsInput States(1110010100)I/O Control(Driver On/Off)Time Set Select(TS1,TS2,TS3)Output States(LZHLHZLHHL)Output Masking(LHXXHXXLXH)Executing a Functional TestThe following steps are required to execute a functional test:1.Define VDD level2.Define input and output levels(VIL/VIH/VOL/VOH)3.Define output current loading(IOL/IOH/VREF)4.Define test cycle time(Testing rate)5.Define input timings and formats for all input pins6.Define output strobe timings for all output pins7.Define start and stop locations for vector memory8.Execute the testInput Signal CreationDUT101100 001101 110001Vector DataLeading TrailingTiming Edge PlacementRZ/RO NRZ/DNRZ SBCVIH1=2.0V VIL1=0.8V VIH2=3.5V VIL2=0.0VFormat DefinitionVoltage LevelsLogic 1Logic 0Logic 1Vector DataEdge TimingRZ FormatRO FormatSBC Forma