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n Phase Margin (PM)n Input Common Mode Rangen Output Swing Range (OSR)n Input/Output Impedance (CIN/ROUT)n Slew Raten Noise In order to decease the power Consumption, IBIAS is only 30nA. To create a symbol of a schematic: From Design-Create Cellview-From Cellview Two methods of simulating Open-Loop Differential Gainis available in ADE (Analog Design Environment) In this method, VP=VCM_IN +x, and VN=VCM_IN-xWhere, VCM_IN is the common voltage, x is a design variables.Setup VN Setup VP To add a model for the simulation From ADE-Setup-Model libraries To create a DC SweepFrom ADE-Analyses-Choose-DC _ _2OUT COM OUT OUT COM OUTV P NV V V VA V V x _ 0|COM OUT OUT xV V Where, Differential Gain is 71.56dBTo obtain VCOM_OUT From Calculator-Special Functions-Value VOUT -VCOM_OUTTo obtain DC gain From Calculator-Special Functions-deriv Setup VN Setup VPIn this method, VP=VCM_IN+ x +VAC, and VN=VCM_INWhere, VCM_IN is the input common voltage, x is a design variables, VAC is a AC voltage for AC Sweep. To add a model for the simulation From ADE-Setup-Model libraries To create a AC SweepFrom ADE-Analyses-Choose-ACFixedFreq 1020logV OUTA VDifferential Gain is 65.56dB The results of the two methods are different, In fact, method 1 is more accurate for DC gain. 11 COUT Ccm V C VAV AV A A A CMRR VC AA CMRRYou can get detail illustration from “CMOS Analog Circuit Design”, Phillip E. Allen, Oxford University Press, Inc. _N P cm COM IN ACV V V V V Where, VCOM_IN is the input common voltage, VAC is a AC voltage for AC Sweep. To add a model for the simulation From ADE-Setup-Model libraries To create a AC SweepFrom ADE-Analyses-Choose-AC 1/CMRR CMRRTo obtain CMRR:From Calculator-1/x1/CMRR and CMRR plot directly. To obtain magnitude Plot of CMRR: From Calculator-dB20 Frequency response of CMRRThe CMRR is 72.14dB at low frequency range.To obtain phase Plot of CMRR: From Calculator-phase 1OUTDDVV PSRRYou can get detail illustration from “CMOS Analog Circuit Design”, Phillip E. Allen, Oxford University Press, Inc. DD DC ACV V V Where, VAC is a AC voltage for AC Sweep, and VDC is a DC voltage To add a model for the simulation From ADE-Setup-Model libraries To create a AC SweepFrom ADE-Analyses-Choose-AC 1/PSRR PSRRTo obtain CMRR:From Calculator-1/x1/PSRR and PSRR plot directly. To obtain magnitude Plot of PSRR: From Calculator-dB20 Frequency response of PSRRThe CMRR is 79.17dB at low frequency range.To obtain phase Plot of PSRR: From Calculator-phase Where, VCM_IN is the input common voltage, VAC is a AC voltage for AC Sweep,And CL is the loading capacitor. VCM_IN VAC The dominant pole is controlled by CL in folded Cascode op amp. To add a model for the simulation From ADE-Setup-Model libraries To create a AC SweepFrom ADE-Analyses-Choose-AC To obtain magnitude Plot of open-loop: From Calculator-dB20open-loop frequency responseThe PM is 74 o when CL is 5pf. To obtain phase Plot of open-loop: From Calculator-phase There have two poles in open-loop frequencyresponse, one is the dominant pole of output net,and the another is the mirror pole caused by active current mirror. Where, x is a design variables and CL is the loading capacitor. To add a model for the simulation From ADE-Setup-Model libraries To create a DC SweepFrom ADE-Analyses-Choose-DC ICMRThe input common-mode range is 04.2V Where, VCM_IN is the input common voltage, x is a design variables. To obtain OSR In this method, VP=VCM_IN +x, and VN=VCM_IN-xWhere, VCM_IN is the common voltage, x is a design variables.Setup VN Setup VP To add a model for the simulation From ADE-Setup-Model libraries To create a DC SweepFrom ADE-Analyses-Choose-DC You can get the left waveform from page 8. OSRThe output swing range is from 842.5mV to 4.381V. PS: OSR is dependence of applications and is not constant. Where, VCM_IN is the input common voltage, VAC is AC voltage for AC Sweep. IN ININ AcI IC j V VCM_IN VAC To add a model for the simulation From ADE-Setup-Model libraries To create a AC SweepFrom ADE-Analyses-Choose-AC The input capacitor is approximate of 5pf OUTOUT OUTVR I The schematic of obtaining open-loop output resistance RO. The equivalent model by using Thevenin form On the op amp. 1 2001200 200V OOUT O VA RR R R A Thus, simulating ROUT and knowing AV allows one to calculate the output resistance RO of the op amp. IOUTVOUT200RR=1GVIN=0V To add a model for the simulation From ADE-Setup-Model libraries To create a TRAN SweepFrom ADE-Analyses-Choose-TRAN IOUT ROUT33 3548 585200 200OUT VO R A MR M The unity-gain configuration places the severest requirements on stabilityand slew rate because its feedback is the largest, resulting in the largest values of loop-gain, and should always be used as a worst-case measurement. The input step magnitude is 2V. To add a model for the simulation From ADE-Setup-Model libraries To create a TranFrom ADE-Analyses-Choose-Tran SR=95.1K V/s VCM_IN VAC The dominant pole is controlled by CL in folded Cascode op amp. To add a model for the simulation From ADE-Setup-Model libraries To create a NoiseFrom ADE-Analyses-Choose-noise Output noise Input-referred noiseTo obtain output noise and input-referred noise:From ADE-results-Direct plot-main form
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