外文翻译--SJA1000--独立的CAN控制器

黑龙江工程学院本科生毕业设计附录A 英文原文SJA1000Stand-alone CAN controller1. INTRODUCTIONThe SJA1000 is a stand-alone CAN Controller product with advanced features for use in automotive and general industrial applications. It is intended to replace the PCA82C200 because it is hardware and software compatible. Due to an enhanced set of functions this device is well suited for many applications especially when systemoptimization, diagnosis and maintenance are important.This report is intended to guide the user in designing complete CAN nodes based on the SJA1000. The report provides typical application circuit diagrams and flow charts for programming.2. OVERVIEWThe stand-alone CAN controller SJA1000 1 has two different Modes of Operation:1.BasicCAN Mode (PCA82C250 compatible).2.PeliCAN Mode.Upon Power-up the BasicCAN Mode is the default mode of operation. Consequently, existing hardware and software developed for the PCA82C250 can be used without any change. In addition to the functions known from the PCA82C250 , some extra features have been implemented in this mode which make the device more attractive. However, they do not influence the compatibility to the PCA82C250.The PeliCAN Mode is a new mode of operation which is able to handle all frame types according to CAN specification 2.0B. Furthermore it provides a couple of enhanced features which makes the SJA1000 suitable for a wide range of applications.2.1 SJA1000 FeaturesThe features of the SJA1000 can be clustered into three main groups:1.Well-established PCA82C200 FunctionsFeatures of this group have already been implemented in the PCA82C250.2.Improved PCA82C200 FunctionsPartly these functions have already been implemented in the PCA82C250. However, in the SJA1000 they have been improved in terms of speed, size or performance.3.Enhanced Functions in PeliCAN ModeIn PeliCAN Mode the SJA1000 offers a couple of Error Analysis Functions supporting diagnosis, system maintenance and optimization. Furthermore functions for general CPU support and System Self Test have been added in this mode.2.2 CAN Node ArchitectureGenerally each CAN module can be divided into different functional blocks. The connection to the CAN bus linesis usually built with a CAN Transceiver optimized for the applications. The transceiver controls thelogic level signals from the CAN controller into the physical levels on the bus and vice versa.The next upper level is a CAN Controller which implements the complete CAN protocol defined in the CAN Specification 8. Often it also covers message buffering and acceptance filtering.All these CAN functions are controlled by a Module Controller which performs the functionality of the application. For example, it controls actuators, reads sensors and handles the man-machine interface (MMI).As shown in Figure 1 the SJA1000 stand-alone CAN controller is always located between a microcontroller and the transceiver, which is an integrated circuit in most cases.Figure 1 CAN Module Set-up2.3 Block DiagramThe following figure shows the block diagram of the SJA1000.The CAN Core Block controls the transmission and reception of CAN frames according to the CAN specification.The Interface Management Logic block performs a link to the external host controller which can be a microcontroller or any other device. Every register access via the SJA1000 multiplexed address/data bus and controlling of the read/write strobes is handled in this unit. Additionally to the BasicCAN functions known from the PCA82C250, new PeliCAN features have been added. As a consequence of this, additional registers and logic have been implemented mainly in this block.Figure 2: Block Diagram SJA1000The Transmit Buffer of the SJA1000 is able to store one complete message (Extended or Standard). Whenever a transmission is initiated by the host controller the Interface Management Logic forces the CAN Core Block to read the CAN message from the Transmit Buffer.When receiving a message, the CAN Core Block converts the serial bit stream into parallel data for the Acceptance Filter. With this programmable filter the SJA1000 decides which messages actually are received by the host controller.All received messages accepted by the acceptance filter are stored within a Receive FIFO. Depending on the mode of operation and the data length up to 32 messages can be stored. This enables the user to be more flexible when specifying interrupt services and interrupt priorities for the system because the probability of data overrun conditions is reduced extremely.3. SYSTEMFor connection to the host controller, the SJA1000 provides a multiplexed address/data bus and additional read/write control signals. The SJA1000 could be seen as a peripheral memory mapped I/O device for the host controller.3.1 SJA1000 ApplicationConfiguration Registers and pins of the SJA1000 allow to use all kinds of integrated or discrete CAN transceivers. Due to the flexible microcontroller interface applications with different microcontrollers are possible.Figure 3 Typical SJA1000 Application3.2 Power SupplyThe SJA1000 has three pairs of voltage supply pins which are used for different digital and analog internal blocks of the CAN controller.1.VDD1 / VSS1: internal logic (digital).2.VDD2 / VSS2: input comparator (analog).3.VDD3 / VSS3: output driver (analog).The supply has been separated for better EME behaviour. For instance the VDD2 can be de-coupled via an RC filter for noise suppression of the comparator.3.3 ResetFor a proper reset of the SJA1000 a stable oscillator clock has to be provided at XTAL1 of the CAN controller,see also chapter 3.4. An external reset on pin 17 is synchronized and internally lengthened to 15 TXTAL. This guarantees a correct reset of all SJA1000 registers (see1). Note that an oscillator start-up time has to be taken into account upon power-up.3.4 Oscillator and Clocking StrategyThe SJA1000 can operate with the on-chip oscillator or with external clock sources. Additionally the CLK OUT pin can be enabled to output the clock frequency for the host controller. Figure 4 shows four different clocking principles for applications with the SJA1000. If the CLK OUT signal is not needed, it can be switched off with the Clock Divider register (Clock Off = 1). This will improve the EME performance of the CAN node.The frequency of the CLK OUT signal can be changed with the Clock Divider Register:CLK OUT = f XTAL / Clock Divider factor (1,2,4,6,8,10,12,14).Upon power up or hardware reset the default value for the Clock Divider factor depends on the selected interface mode (pin 11). If a 16 MHz crystal is used in Intel mode, the frequency at CLK OUT is 8 MHz. In Motorola mode a Clock Divider factor of 12 is used upon reset which results in 1,33 MHz in this case.Figure 4 Clocking Schemes3.4.1 Sleep and Wake-upUpon setting the Go To Sleep bit in the Command Register (BasicCAN mode) or the Sleep Mode bit in the Mode Register (PeliCAN mode) the SJA1000 will enter Sleep Mode if there is no bus activity and no interrupt is pending. The oscillator keeps on running until 15 CAN bit times have been passed. This allows a microcontroller clocked with the CLK OUT frequency to enter its own low power consumption mode.If one of three possible wake-up conditions occurs the oscillator is started again and a Wake-up interrupt is generated. As soon as the oscillator is stable the CLK OUT frequency is active.3.5 CPU InterfaceThe SJA1000 supports the direct connection to two famous microcontroller families: 80C51 and 68xx. With the MODE pin of the SJA1000 the interface mode is selected.Intel Mode: MODE = high.Motorola Mode: MODE = low.The connection for the address/data bus and the read/write control signals in both Intel and Motorola mode is shown in Figure 5. For Philips 8-bit microcontrollers based on the 80C51 family and the 16-bit microcontrollers with XA architecture the Intel Mode is used.For other controllers additional glue logic is necessary for adaptation of the address/data bus and the control signals. However, it has to be made sure that no write pulses are generated during power-up. Another possibility is to disable the CAN controller with a high-level on the chip select input in this time.Figure 5 CPU Interface of the SJA10003.6 Physical Layer InterfaceFor compatibility purposes with the PCA82C250, the SJA1000 includes an analog receive input comparator circuit. This integrated comparator can be used if the transceiver function is realized with discrete components.Figure 6 SJA1000 Receive Input ComparatorIf an external integrated transceiver circuit is used and the comparator bypass function is not enabled in the Clock Divider Register, the RX1 input has to be connected to a reference voltage of 2.5V (reference voltage output of existing transceiver circuits). Figure 6 shows the equivalent circuits for both configurations:CBP = active and CBP = inactive. Additionally the path for the wake-up signal is drawn.For all new applications where an integrated transceiver circuit is used, it is recommended to activate the comparator bypass function of the SJA1000 (Figure 7). If this function is enabled, a schmitt-trigger input is used and the internal propagation delay TD2 is much shorter as the delay TD1. of the receive comparator. This has a positive impact on the maximum bus length6. Additionally, it will reduce the supply current in sleep mode significantly.Figure 7 Standard application with integrated transceiver circuit附录B 英文翻译SJA1000独立的CAN控制器1.介绍控制器局部网CAN是一个串行的异步的多主机的通讯协议SJA1000是一个独立的CAN控制器它在汽车和普通的工业应用上有先进的特征由于硬件和软件的兼容它将会替代PCA82C250。它与PCA82C250相比具有更先进的特征因此特别适合于轿车内的电子模块传感器制动器的连接和通用工业应用中特别是系统优化系统诊断和系统维护时特别重要。本文倾向于在设计SJA1000为基础的CAN节点上引导用户同时还提供典型的应用电路图和用于编程的流程图。2.概述独立的CAN控制器SJA1000有2个不同的操作模式：1.BasicCAN 模式(PCA82C250兼容)。2.PeliCAN 模式。上电时BasicCAN模式是默认的操作模式因此已经使用PCA82C250开发出的硬件和软件可以直接被SJA1000使用而不用作任何修改PeliCAN 模式是操作的新模式它能够处理所有的CAN2.0B定义的帧类型而且它还提供一些增强功能使SJA1000能应用于更宽的领域。2.1 SJA1000特征SJA1000的特征能分成3组：1.已建立好的PCA82C250功能这组的特征在 PCA82C250里已经生效。2.提高的PCA82C200功能部份这些功能在PCA82C250里已经生效但是在SJA1000里它们在速度大小和性能方面已得到提高。3.在PeliCAN模式里的增强功能在PeliCAN 模式里SJA1000支持一些错误分析功能如支持系统诊断系统维护系统优化而且这个模式里也加入了对一般CPU的支持和系统自身测试的功能。2.2 CAN 节点结构一般来说每个CAN模块能够被分成不同的功能块CAN总线的连接通常由被优化的CAN收发器建立收发器控制逻辑电平信号从CAN控制器到达总线上的物理层反之亦然。上面一层是一个CAN控制器它执行在CAN规约里定义的CAN协议它通常用于信息缓冲和验收滤波。而所有这些CAN功能都被一个模块控制器控制它用于执行功能性的应用例如控制调节器读传感器和处理人机接口MMI。如图1所示，SJA1000独立的CAN控制器总是位于微型控制器和收发器之间在一般情况下这个控制器是一个集成电路。图1 CAN模块装置2.3方块图下图是SJA1000的方块图。图2 SJA1000的方块图根据CAN规约CAN核心模块控制CAN帧的发送和接收。接口管理逻辑完成对外部主控制器的连接该控制器能可以是微型控制器或其他器件经过SJA1000复用的地址/数据总线访问寄存器和控制读/写选通信号都在这里处理另外除了PCA82C200已有的BasicCAN功能还加入了一个新的PeliCAN功能因此附加的寄存器和逻辑电路主要在这块里生效。SJA1000的发送缓冲器能够存储一个完整的信息扩展的或标准的无论什么时候主控制器初始化发送接口管理逻辑会迫使CAN核心块从发送缓冲器读CAN 信息。当收到一个信息时CAN核心块将串行位流转换成用于验收滤波器的并行数据通过这个可编程的滤波器SJA1000能确定哪些信息实际上被主控制器收到。所有收到的信息由验收滤波器接收并存储在接收FIFO储存信息的多少由工作模式决定而最多能存储32个信息因为数据溢出的可能性被大大降低这使用户能更灵活地指定中断服务和中断优先级。3.系统为了连接到主控制器SJA1000提供一个复用的地址/数据总线和附加的读/写控制信号SJA1000能被看作外围存储器并为主控制器映射I/O设备。3.1 SJA1000应用SJA1000的寄存器和管脚配置允许它使用于各种各样的集成的或分立的CAN收发器这使不同微控制器之间的接口能够被灵活运用。一个包括80C51微型控制器和PCA82C250收发器的典型SJA1000应用图如图3所示CAN控制器功能作为一个时钟源复位信号由外部复位电路产生在这个例子里SJA1000的片选由微控制器的P2.7口控制否则这个片选输入必须接到VSS也可以通过地址解码控制例如当地址/数据总线用于其他外围器件。图3 典型的SJA1000应用3.2 电源SJA1000有三组电源引脚用于CAN控制器内部不同的数字和模拟模块：1.VDD1/VSS1内部逻辑数字。2.VDD2/VSS2输入比较器模拟。3.VDD3/VSS3输出驱动器模拟。为了更好EME电源应该分开例如用于比较器的VDD2可一个RC滤波器解耦来抑制噪音。3.3 复位为了得到一个恰当的复位一个稳定的振荡器时钟必须接在在CAN 控制器的XTAL1管脚上见3.4章引脚17上的外部复位需要被同步并被内部延长到15个TXTAL这保证了SJA1000所有的寄存器正确的复位要注意的是上电时必须要考虑振荡器的起振时间。3.4 振荡器和时钟策略图4 时钟方案上电时或硬件复位时钟分频因子的默认值取决于所选的接口模式引脚11如果使用16MHz的晶振在Intel模式下CLK OUT 的频率是8 MHz在Motorola模式复位之后的时钟分频因子是12 这种情况会产生1.33MHz。3.4.1 睡眠和唤醒置位命令寄存器中的睡眠位BasicCAN模式或模式寄存器PeliCAN模式的睡眠模式位后如果没有总线活动和中断等待SJA1000就会进入睡眠模式振荡器保持运行直到已过了15个CAN位此时允许微型控制器与CLKOUT频率同步来进入低功耗模式。图5 SJA1000的CPU时钟接口如果三个唤醒条件之一发生,振荡器会再次启动并产生一个唤醒中断振荡器稳定下来后时CLKOUT 频率被激活。3.5 CPU接口SJA1000支持对两个著名的微型控制器系列的直接连接80C51 68xx通过SJA1000 的MODE引脚可选择接口模式：1.Intel 模式：MODE 高2.Motorola 模式: MODE 低在Intel模式和Motorola模式里地址/数据总线和读/写控制信号的连接如图5 所示飞利浦基于80C51系列8 位微控制器和带有XA结构的16位微型控制器都使用Intel模式。为了和其他控制器的地址数据总线和控制信号匹配必须要附加逻辑电路但是必须确保在上电期间不产生写脉冲另一个方法在这个时候使片选输入高电平CAN控制器无效。3.6 物理层接口为了和PCA82C200 兼容SJA1000 包括一个模拟接收输入比较器电路如果收发器的功能由分立元件实现这个集成的比较器就能使用。如果外部集成收发器电路有效而比较器旁路功能在时钟分频寄存器里无效RX1必须被连接到2.5V的参考电压上现存的收发器参考电压输出图6显示了两种设置的相应电路：CBP激活CBP非激活另外唤醒信号的通道被引出。图6 SJA1000接收输入比较器一个集成的收发器电路使用所有的新应用 都建议激活SJA1000的比较器旁路功能图7 如果这个功能被使能施密特触发器有效内部的传播延迟TD2比接收比较器延迟的TD1要小得多这在最大总线长度上有积极的影响另外它在休眠模式里将显著地降低电流。图7 带有集成收发电路的标准应用12