外文翻译--ST7536介绍

ST7536 introduceBy Joel HULOUXI- INTRODUCTION TO THE ST7536The ST7536 is a half duplex synchronous FSK-modem,and has been designed to operate on powerline networks.For a complete communication system, a micro-controller and a powerline-interface (PLI) are needed (see Figure 1).Such a system is able to transmit and receive on 4 different channels with 2 differentdata rates (600 and 1200 baud).The baudrate (BRS) and channel (CHS) selection is made,according to the Table.The ST7536 is a half duplex modem,as it has two operation modes;receive or transmit data.The mode selection is made with a Rx/Tx control input.Data input and output are related to the clock signal;its a synchronous modem. This clock signal is generated by the ST7536.Only a few external components have to be added for full operation of the ST7536:a crystal, four resistors and five capacitors.II- ST7536 DESCRIPTIONThe ST7536 is a single chip modem;all the electrical circuits needed for a complete modem are inside the chip. The modem is available in 28 pins PLCC (see Figure 2).In transmit mode the Transmit Data (TxD) is sampled on the positive edge of the clock (CLR/T).Then the data enters the FSK modulator. The frequency on which this modulator operates is set by the time base and control logic. In normal operation the multiplexer(MUX) selects the FSK modulator signal to be send to the transmit filter.This filter is a switched capacitor band-pass filter. Thetime base and controllogic uses the Automatic Frequency Control (AFC) to set this filter at the transmit frequency, corresponding to the selected channel.After filtering, the transmitsignal is sent to an Automatic Level Control (ALC).This control is used to overcome problems with line impedance variations.The powerlines on which the modem has to operate, have variations in their line characteristics,which are very frequent and totally unpredictable.The automatic level control uses a feed back signal (ALCI) from the powerline interface to adjust the transmit output (ATO).In receive mode the signal enters the chip on the Receive AnalogInput(RAI).The received signal is filtered in the receive band-pass filter. Its just like the transmit filter,a switched capacitor filter.The automatic frequency control is used to set it on the right frequency. After being amplified the signal is down converted and filtered in the intermediate frequency band-pass filter.The resulting signal is sent to the FSK demodulator. The coupling of the intermediate frequency filter output (IFO) to the FSK DEModulator Input(DEMI) is made by an externalcapacitor which cancelsan even tualoff set voltage.A clock recovery circuit extracts the receive clock (CLR/T) from the demodulated output (RxDEM) of the FSK demodulator. Synchronous received data (RxD) is delivered on the positive edge of the clock.A time base section delivers all the internal clock signals from a crystal oscillator running at 11.0592MHz.The crystal is connected between the XTAL1 and XTAL2 pins.It is also possible to provide directly a clock signal on XTAL1 instead of using a crystal.To debug the chip and test external circuits the ST7536 provides some test options. The transmit band-pass filter can be observed using a direct input on the filter. This input (TxFI) is selected by the multiplexer if TEST4 = 1. The Receive bandpass Filter Output (RxFO) is provided at pin 25.Finally the clock recovery can be observed when TEST1 = 1. In this case the TEST3 input gives a direct input to the clock recovery block.III- ST7536 PIN DESCRIPTIONThe pin description is not given in numerical order,but the pins are described in relation with their function and consequentlysometimes with other pins.- power supply input- channel selection- crystal oscillator input- AFCF stabilisation- automatic level control input- data input and output- test inputs- IFO/DEMI output/input- transmit output and receive input- Rx/Tx control input- reset inputIII.1- Power Supply Input- Pin 8 (DGND): Digital ground (0V)- Pin 9 (DVDD): Digital positive supply voltage (+5V)- Pin 18 (DVSS): Digital negative supply voltage (-5V)- Pin 21 (AVSS): Analog negative supply voltage (-5V)- Pin 22 (AGND): Analog ground (0V)- Pin 23 (AVDD): Analog positive supply voltage (+5V)Internally the ST7536 has separated power supplies:The digital andanalog circuit sare separated.Externally the power supplies should be connected together.For decoupling,both the positive and negative supplies are decoupled with 2 capacitors.C6 and C7 decouple the positive,C8 and C9 the negative supplies.For proper operation the digital positive supply voltage should be decoupled with a capacitor(C10)mounted close to Pin9.C6,C8 and C10 are100nF/16Vceramic capacitors,C7 and C9 10uF/16V tant alcapacitors (seeFigure 3). III.2 - Channel Selection- Pin 15 (CHS): Channel selection input- Pin 16 (BRS): Baudrate selection inputBoth inputs are digital inputs (0/+5V). The ST7536 operates with two bit rates: 600 and 1200 baud. These bit rates are selected with pin 16 (BRS). For both bit rates the ST7536 offers two channels,which are selected with pin 15 (CHS).Alogical”0” is represented by 0V, a”1”by +5V. R1 and R2 are pull-down resistors,creating a logical”0”.Closing a switch gives a”1”.The selection is made according to Table 1.III.3 - Crystal Oscillator Input- Pin 13 (XTAL2): Crystal oscillator output- Pin 14 (XTAL1): Crystal oscillator inputThe internal crystal oscillator of the ST7536 needs an external crystal. This one should be a 11.0592MHz crystal. Two capacitors (C1 and C2) have to be added for proper operation. They are typically 22pF/10V ceramic capacitors. It is also possible to connect directly a clock signal to the oscillator input, in this case the crystal and the capacitors should be removed.On the application board this option is notused. The ST7536 clock signal is the time reference of the system.III.4 - AFCF Stabilisation- Pin 17 (AFCF) : Automatic frequency control outputIn the ST7536 an automaticcontrol section adjusts the central frequency of the receive and transmit band-passfilters. The stabilityof this sectionhas to be ensured with an external RC network.III.5 - Automatic Level Control Input- Pin 27 (ALCI): Automatic level control input. The output stage of the transmit path consists of an automatic level control (ALC).It offers the possibility to keep the output voltage of the power amplifier independent of variations of the powerline network. The impedance of these networks can be anywhere in the range of 5-100.If the impedance of the powerline changes,the outputof theamplifier will change.With the ALC input it is possible to correct these output variations. To control the output of the powerline interface a feed-back signal is needed. This signal is sent through an amplifier. The automatic level control can decrease the maximum transmit output in 32 steps of 0.84dB. The gain range is 0dB-26dB. A peak detection is done on the signal presented on the ALC Input and the ALCcompares it to two reference voltages, VT1 (1.87V) and VT2 (2.12V).If max. VALCI VT1 the next gain is increased by 84dB.If VT1 max. VALCI VT2 there is no gain change.If VT2 max. VALCI the next gain is decreased by 0.84dB.The gain of the feed-back amplifier is such that the feed-back signal peak voltage falls between VT1 and VT2.III.6 - Data Input and Output- Pin 5 (RxD): Synchronous receive data output- Pin 6 (CLR/T): Receive and transmit clock- Pin 7 (RxDEM): Demodulated data output- Pin 12 (TxD): Transmit data inputThe ST7536 is a synchronous modem; data input and output are related to the clock (CLR/T). In transmit mode the ST7536 generates this clock signal. The transmit data are sampled on the positive edge of CLR/T. Therefore the TxD should be valid at that moment.In receive mode the demodulated (receive) data is available at pin 7(RxDEM). A clock recovery circuit extracts the clock signal from the demodulated data and delivers synchronous data (RxD) on the positive edge of CLR/T. On the application board the RxDEM data output is not used. All the data signals from and to the ST7536 (RxD, TxD) are related to the clock (CLR/T) (see Figure 8).III.7 - Test Inputs- Pin 3 (TEST4): Test input,with a”1”on this pin the multiplexer selects thetransmit band-pass filter input(TXFI).- Pin 4 (TEST3): Test input which gives a direct acces to the clock recovery circuit.This input is selected when TEST1=”1”.- Pin 10 (TEST1): Test input,a”1”on this pin cancels the automatic switching from transmit to receive mode, and validates the TEST3 input to the clock recovery circuit.- Pin 11(TEST2): Test input,a”1”on this pin reduces the automatic switching time (from transmit to receive mode) to 1.48ms.On the applicationboard TEST 2/3/4 are not used,and Pins 3, 4, and 11 are thereforeset at 0V.With a switch TEST1 can be set at”0”or”1”.See also the Rx/Tx control input.III.8- IFO/DEMIOutput/Input- Pin 19 (IFO): Intermediate frequency filter output- Pin 20 (DEMI): FSK demodulator inputThe connection between the intermediate frequency filter output and the FSK demodulator input should be made externally with a capacitor (C5, 1uF/10V).III.9 - Transmit Output and Receive Input- Pin 24 (RAI): Receive analog input- pin 28 (ATO): Analog transmit outputPin 24 is the receive input of the ST7536. The receive output of the powerline interface should be connected to this pin.The maximum input voltageis 2VRMS. The receive sensitivity of the ST7536 is 2mVRMS on channel 1 and 2 (600 baud),and 3mVRMS on channel 3 and 4 (1200 baud).Pin 28 is the transmit output of the ST7536. The transmit input of the powerline interface should be connected to this pin. The ATO output is regulated by the ALCI circuit. The maximum output voltage is 3.5VPP. The second harmonic distortion is about -53dB.III.10 - Rx/Tx Control Input- Pin 1 (Rx/Tx): Receive or transmit mode selection input .The ST7536 is a half duplex modem and has therefore two operation modes: receive and transmit. This mode selection is done with the Rx/Tx input. The transmit mode is selected when Rx/Tx is”0”.If Rx/Tx is held a”0”longer than 3 seconds, the ST7536 switches back to receive mode. To set the ST7536 again in transmit mode, Rx/Tx should be held at”1”for a minimum of 3s before being set to”0”.The carrier activation time is 1msec. To be able to observe the transmit output of the ST7536 on the power line interfacefor a longer time than3 seconds it is possible to use the test 1 Input. If this input is set at”1”the automatic switching is disactivated. Then it is possible to transmit a signal but not to receive.III.11 - Reset Input- Pin 2 (RESET): Logic reset and power-down input When this input is set at”0”the ST7536 is in power-down mode.All the internal logic is then reset.For normal operation this input should be setat”1”.On the application board this input is controlled by the micro-controller.Technical Data Sheet SSC P300 PL Network Interface Controller Features-Enables Low-cost CEBus compatible products-EIA-600 (CEBus) Data Link Layer services-EIA-600 Physical Layer transceiver-Spread Spectrum Carrier Power Line technology-SPI Host Processor interface-Data Link, Controller, and Monitor modes-Single +5 Volt power supply requirement-20 pin SOIC packageIntroductionThe Intellon SSC P300 PL Network Interface Controller is a highly integrated power line transceiver and channel access interface for implementing CEBus compatible products.The SSC P300 provides the Data Link Layer (DLL) control logic for EIA-600 channel access and communication services, a Spread Spectrum Carrier(SSC) power line transceiver, signal conditioning circuitry, and a serial peripheral interface (SPI) compatible host interface. A minimum of external circuitry is required to connect the SSC P300 to the power line. Superior performance is achieved using the SSC P300 in conjunction with the SSC P111 Media Interface IC. The SSC P300 is used with a host microcontroller to construct CEBus compatible products, and serves as the basic communications element in a variety of low-cost power line networking applications.The inherent reliability of SSC signaling technology and incorporation of basic Data Link functionality combine to provide substantial improvement in network and communication performance over other power line communication methods. The SSC P300 also makes an excellent low cost network interface for twisted pair and DC power systems. A typical CEBus power line node using the SSC P300 is illustrated below.SSC P300 Node Block DiagramVDD DC Supply Voltage -0.3to 7.0VVIN Input Voltage at any Pin VSS-0.3 to VDD+0.3VTSTG Storage Temperature -65 to +150CTL Lead Temperature(Soldering,10 seconds)300CNote:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages.Recommended Operating ConditionsVDD DC Supply Voltage 4.5、5.0、5.5VFOSC Oscillator Frequency 12 +/- 0.01% MHzTA Operating Temperature -40、+25、+85CHumidity non-condensingElectrical CharacteristicsConditions:VDD = 4.5 to 5.5 V T=-40 to +85CSymbol Parameter Min Typical Max UnitsVOH Minimum High-level Output Voltage 2.4VVOL Maximum Low-level Output Voltage (1) 0.4VVIH Minimum High-level Input Voltage 2.0VVIL Maximum Low-level Input Voltage 0.8VHys Minimum Input hysteresis 350 mVIIL Maximum Input Leakage Current +/-10AvSO SSC Signal Output Voltage (2) 4 VP-PIDD Total Power Supply Current 25 mALatchup (3) 150 mANotes:1. IOL = 2 mA2. ZL = 2K | 10 pF3. JEDEC JC -40.2SSC PL P300 Network Interface ControllerSSC P300 Pin Assignments1 4MHZ 4 MHz clock out 4 MHz clock output available for host microcontroller.2 CS*Chip select Digital input, active low. Enables serial peripheral interface.3 VSSD Digital ground Digital ground reference.4 XIN Crystal input Connected to external crystal to excite the ICs internaloscillator and digital clock.5 XOUT Crystal output Connected to external crystal to excite the ICs internal oscillator and digital clock.6 VDDD Digital supply 5.0 VDC +/- 10% digital supply voltage with respect to VSSD.7 INT* Interrupt Digital output, active low. Attention request to hostmicrocontroller.8 SCLK SPI data clock Serial peripheral interface clock input from hostmicrocontroller.9 SDO SPI data out Data output to host microcontroller serial peripheral interface. SDO istristate when CS* is false.10 SDI SPI data in Data input from host microcontroller serial peripheralinterface.11 TS Tristate Active low digital output signal driven from the same internalsignal that enables the output amplifier.12 RST* Reset Active low digital input.13 VSSA Analog ground Analog ground reference.14 SO Signal output Analog signal output. Tristate enabled with internal TS signal.15 C2 Capacitor 2 Connection for 680pF capacitor to ground.16 C1 Capacitor 1 Connection for 680pF capacitor to ground.17 SI Signal input Analog signal input.18 VDDA Analog supply 5.0 VDC +/- 10% analog supply voltage with respect to VSSA.19 TP0 Test point 0 Reserved pin for testing.20 VSSD Digital ground Digital ground reference.SSC PL P300 Network Interface ControllerSSC P300 Node OverviewThe SSC P300 is designed to meet the needs of products requiring EIA-600 compatibility. As the SSC P300 uses fewer interface signals than the SSC P400 does, a lower cost host (microcontroller) may be used. Coupling the lower cost host with the low cost of the SSC P300, an EIA-600 compliance node can be added to cost sensitive products. The SSC P300 can transmit and receive all four Data Link services defined in the EIA-600 standard, which allows the designer to select the best Data Link service for the job.As seen in the block diagram on page 1, a typical node consists of three sections: The first section is the host microprocessor or microcontroller, which is responsible for communicating with the SSC P300 and performing application specific tasks. The second section is the SSC P300 itself. It is responsible for resource intensive.Data Link functions and Physical layer services of the protocol. Specific DLL services include transmission and reception of packets, byte-to-symbol conversion for transmitted packets, symbol-to-byte conversion for received packets, transmit channel access (based on packet priority and EIA-600 access rules), and CRC generation and checking. The last section is the power line analog functions. These functions include: coupling the signal frequencies onto the medium, amplification of the transmitted signal to drive the impedance of the medium, and input filtering of the incoming signal.The host communicates with the SSC P300 by issuing commands. These commands provide for the initialization and verification of the nodes operating mode and addresses, for the transmission and reception of packets, and for the return of status information. In general, the host must provide the following functions in order to utilize the SSC P300:1. Initialization routine.2. Routine to write commands out to the chip.3. Routine to read data from the chip.4. Interrupt service routine.The SSC P300 can be placed into one of three operating modes:Data Link Layer (DLL) mode, Controller(CON) mode,and Monitor(MON) mode. In the DLL mode, the P300 will manage all address matching, and timer resources.In the CON mode, the P300 converts the incoming signal into bytes.It becomes the responsibility of the host to manage address matching and timer resources. The MON mode monitors the medium. Any packet detected on the medium is passed up to the host regardless of the packets address or type.ST7536介绍Joel HULOUX著1、ST7536 的介绍ST7536是一个半双工同步FSK调制解调器,并且对于设计和操作电力线网络是很有帮助的。对于一个完整的通信系统,微型控制器和电力线接口(PLI)是必要的。这样系统能在4种不同频道上以2种不同的数据率(600和1200波特)传送和接收信号。波特率(BRS)和频道(CHS)选择在此时被执行。ST7536是一个半双工调制解调器,因为它有二个操作方式，接收或传送数据。模式选择用Rx/或用Tx作为控制输入。数据输入和输出是与时钟信号有关的。它是一个同步调制解调器。这个时钟信号由ST7536所引起。几个外在分组都必须增加对ST7536的进行设置:一个晶振, 四个电阻器和五台电容器。2、ST7536 描述ST7536是一个具有唯一一个芯片的调制解调器；所有电子电路需要有一个完整的调制解调器处在芯片里面。调制解调器是在28个串口可利用的PLCC。传送数据的方式(TxD)被抽样在时钟的正面边缘(CLR/T)。然后数据进入FSK调制器。这个调制器所需的频率被设置在时间基准和控制逻辑上。在正常运行多重通道(MUX)选择的FSK调制器信号是送到传送过滤器的。过滤器是一台被交换的电容器带通滤波器。时间基准和控制逻辑的用途是所谓的自动频率控制(AFC)的设置。这过滤器以传送频率, 对应于选择的频道，在过滤以后,传输信号被送到自动电平控制(ALC)电路。这种控制的使用是为了克服有线的问题阻抗变异。调制解调器必须运用在电力线耦合下来的信号,变异的出现是在于他们的线性特征发生改变,有些是非常频繁而且是完全变化莫测的。自动电平控制使用一个反馈信号(ALCI) 从电力线接口调整传送信号(ATO)。在接收信号进入芯片时分析其输入的方式(RAI)。接收的信号通过接收带通滤波器进行过滤。它就像传送过滤器, 等效于电容过滤器。自动频率控制使用设置它在正确的频率。在被放大以后信号是在转换和过滤下通过中频带通滤波器。收到的信号寄发到FSK解调器。中频过滤器输出信号的联结(IFO)对FSK 解调器输入(DEMI)由均匀集合电压做改变。时钟补救电路时钟(CLR/T)是从被解调的输出信号提供的。同步被接收的数据(RxD)被设置在正面时钟的边缘。时间基本的部分提供所有内部时钟信号从一台晶体控制振荡器提供并运行在11.0592MHz。晶振是运行于XTAL1和XTAL2 之间。它还可能直接地从XTAL1提取时钟信号而不是使用晶振。调试芯片和测试外部ST7536提供一些测试选择。传送带通滤波器直接通过过滤器被观察。这输入(TxFI) 由多重通道选择在TEST4=1。接收带通滤波器输出信号(RxFO)被设置在串口25。最后时钟补救可能被设置在TEST1=1。TEST3输入在这种情况下直接根据输入时钟设置。3、ST7536 PIN 描述串口的描述不需要数字次序,但串口在与其他串口之间的联系被描述。- 电源输入- 频道选择- 晶体控制振荡器输入- AFCF平稳- 自动电平控制输入- 数据输入和输出- 测试输入- IFO/DEMI输出输入- 传送输出和接收输入- Rx/Tx控制输入- 重新设置输入3.1 电源输入- Pin 8 (DGND): 数字式接地(0V)- Pin 9 (DVDD): 数字式正极供应 电压(+5V)- Pin 18 (DVSS): 数字式负极供应 电压(-5V)- Pin 21 (AVSS): 模式负极供应 电压(-5V)- Pin 22 (AGND): 模式接地(0V)- Pin 23 (AVDD): 模式正极供应电压(+5V)ST7536内部分离了电源:数字式分析电路被分离。外部电源应该一起被连接。正极和负极供应与2台电容器分离。C6和C7由正极供应,C8和C9负性供应。适当的操作数字式正极电源电压应该被分离。C6,C8和C10是100nF/16V的电容器,C7 和C9 是10mF/16的电容器。3.2 频道的选择PIN15（CHS）：频道选择输入PIN16（BRS）：波特率选择输入以上的两种输入都是数字输入（0/+5V）。这个ST7536设置在两种比特率上：（600和1200BAUD）。这些比特率是由PIN16（BRS）来选择的。对于两种比特率ST7536通过PIN15提供两种频道。非逻辑0通过0V来描述，而非逻辑1是通过+5V来描述的。R1和R2是被电阻器来隔离的，创造一个逻辑0，而关闭给予的非逻辑1。3.3 晶体振荡器的输入Pin 13(XTAL2):晶体振荡器输出Pin 14（XTAL1）:晶体振荡器输入