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第2章EDA设计流程及其工具课程讲义,合肥工业大学彭良清,本章内容,EDA设计的一般步骤常用EDA工具软件使用MAX+PLUSII软件设计过程使用QuartusII软件设计过程硬件设计和软件设计的时间协调设计的几个问题,EDA设计的一般步骤,电路的模块划分设计输入器件和引脚指配编译与排错功能仿真和时序仿真编程与配置，设计代码的芯片运行,电路的模块划分,人工根据电路功能进行模块划分合理的模块划分关系到电路的性能实现的难易程度根据模块划分和系统功能确定：PLD芯片型号模块划分后，就可以进行具体设计了,设计输入,一般EDA软件允许3种设计输入：HDL语言电路图波形输入,何为？器件和引脚指配,器件指配为设计输入选择合适的PLD器件型号何谓引脚指配将设计代码（图形）中的端口（PORT）和PLD芯片的引脚（PIN）对应起来的.指配文件MAX+PLUSII：“*.acf”QuartusII：“*.qsf”,器件和引脚指配的方法,方法有2种在软件的菜单界面中指配修改指配文件（是文本文件）,菜单界面中指配,修改指配文件,CHIPio_2d_lockBEGIN|iVD:INPUT_PIN=7;|iHD:INPUT_PIN=8;|iDENA:INPUT_PIN=6;|iCLK:INPUT_PIN=211;|oCLK:OUTPUT_PIN=237;|oVD:OUTPUT_PIN=234;|oHD:OUTPUT_PIN=233;|oDENA:OUTPUT_PIN=235;.DEVICE=EPF10K30AQC240-2;END;.,编译与排错,编译过程有2种，作用分别为：语法编译：只是综合并输出网表编译设计文件，综合产生门级代码编译器只运行到综合这步就停止了编译器只产生估算的延时数值完全的编译：包括编译，网表输出，综合，配置器件编译器除了完成以上的步骤，还要将设计配置到ALTERA的器件中去编译器根据器件特性产生真正的延时时间和给器件的配置文件,功能仿真和时序仿真,仿真的概念：在设计代码下载到芯片前，在EDA软件中对设计的输出进行波形仿真。常用的2种仿真模式功能仿真对设计的逻辑功能进行仿真时序仿真对设计的逻辑功能和信号的时间延时进行仿真。仿真前还要做的工作输入信号的建立,QuartusII软件中关于仿真的原文,2种仿真文件,矢量波形文件：aVectorWaveformFile(.vwf)文本矢量文件atext-basedVectorFile(.vec),编程与配置,最后，如果仿真也正确的话，那我们就可以将设计代码配置或者编程到芯片中了编程的文件类型对于CPLD或者EPC2，ECS1等配置芯片，编程文件扩展名为：“*.POF“配置的文件类型对于FPGA芯片，配置文件扩展名为：“*.SOF“,硬件设计和软件设计的时间协调,软件模块划分，器件的初步信号确定（主要是根据需要的I/O引脚的数量）软件设计，硬件外围电路设计和器件选择软件仿真仿真完成后，器件信号的重新审核，进行硬件电路图设计综合调试完成,设计的几个问题,如何组织多个设计文件的系统？，项目的概念。时钟系统如何设计？电路的设计功耗高速信号的软件和硬件设计,Theend.,以下内容为正文的引用，可不阅读。,常用EDA工具软件,EDA软件方面，大体可以分为两类：PLD器件厂商提供的EDA工具。较著名的如：Altera公司的Max+plusII和QuartusII、Xilinx公司的FoundationSeries、Latice-Vantis公司的ispEXERTSystem。第三方专业软件公司提供的EDA工具。常用的有：Synopsys公司的FPGACompilerII、ExemplarLogic公司的LeonardoSpectrum、Synplicity公司的Synplify。第三方工具软件是对CPLD/FPGA生产厂家开发软件的补充和优化，如通常认为Max+plusII和QuartusII对VHDL/VerilogHDL逻辑综合能力不强，如果采用专用的HDL工具进行逻辑综合，会有效地提高综合质量。,ALTERA公司的EDA合作伙伴,硬件描述语言：起源,是电子电路的文本描述。最早的发明者：美国国防部，VHDL,1983大浪淘沙，为大者二：VHDL和VerilogHDL其他的小兄弟：ABEL、AHDL、SystemVerilog、SystemC。,一个D触发器的VHDL代码例子,-VHDLcodeposition:p83_ex4_11_DFF1-LIBARYIEEE;-USEIEEE.STD_LOGIC_1164.ALL;ENTITYDFF1ISPORT(CLK:INBIT;D:INBIT;Q:OUTBIT);ENDENTITYDFF1;ARCHITECTUREbhvOFDFF1ISBEGINPROCESS(CLK)BEGINIFCLKEVENTAND(CLK=1)AND(CLKLAST_VALUE=0)THEN-严格的CLK信号上升沿定义Q,CompilerNetlistExtractor（编译器网表提取器）,TheCompilermodulethatconvertseachdesignfileinaproject(oreachcellofanEDIFInputFile)intoaseparatebinaryCNF.Thefilename(s)oftheCNF(s)arebasedontheprojectname.ExampleTheCompilerNetlistExtractoralsocreatesasingleHIFthatdocumentsthehierarchicalconnectionsbetweendesignfiles.Thismodulecontainsabuilt-inEDIFNetlistReader,VerilogNetlistReader,VHDLNetlistReader,andconvertersthattranslateADFsandSMFsforusewithMAX+PLUSII.Duringnetlistextraction,thismodulecheckseachdesignfileforproblemssuchasduplicatenodenames,missinginputsandoutputs,andoutputsthataretiedtogether.返回,DatabaseBuilder(数据库构建器):,TheCompilermodulethatbuildsasingle,fullyflattenedprojectdatabasethatintegratesallthedesignfilesinaprojecthierarchy.TheDatabaseBuilderusestheHIFtolinktheCNFsthatdescribetheproject.BasedontheHIFdata,theDatabaseBuildercopieseachCNFintotheprojectdatabase.EachCNFisinsertedintothedatabaseasmanytimesasitisusedwithintheoriginalhierarchicalproject.Thedatabasethuspreservestheelectricalconnectivityoftheproject.TheCompilerusesthisdatabasefortheremainderofprojectprocessing.EachsubsequentCompilermoduleupdatesthedatabaseuntilitcontainsthefullyoptimizedproject.Inthebeginning,thedatabasecontainsonlytheoriginalnetlists;attheend,itcontainsafullyminimized,fittedproject,whichtheAssemblerusestocreateoneormorefilesfordeviceprogramming.Asitcreatesthedatabase,theDatabaseBuilderexaminesthelogicalcompletenessandconsistencyoftheproject,andchecksforboundaryconnectivityandsyntacticalerrors(e.g.,anodewithoutasourceordestination).Mosterrorsaredetectedandcanbeeasilycorrectedatthisstageofprojectprocessing.返回,LogicSynthesizer,TheCompilermodulethatsynthesizesthelogicinaprojectsdesignfiles.UsingthedatabasecreatedbytheDatabaseBuilder,theLogicSynthesizercalculatesBooleanequationsforeachinputtoaprimitiveandminimizesthelogicaccordingtoyourspecifications.ForprojectsthatuseJKorSRflipflops,theLogicSynthesizercheckseachcasetodeterminewhetheraDorTflipflopwillimplementtheprojectmoreefficiently.DorTflipflopsaresubstitutedwhereappropriate,andtheresultingequationsareminimizedaccordingly.TheLogicSynthesizeralsosynthesizesequationsforflipflopstoimplementstateregistersofstatemachines.AnequationforeachstatebitisoptimallyimplementedwitheitheraDorTflipflop.Ifnostatebitassignmentshavebeenmade,orifanincompletesetofstatebitassignmentshasbeencreated,theLogicSynthesizerautomaticallycreatesasetofstatebitstoencodethestatemachine.Theseencodingsarechosentominimizetheresourcesused.返回,Fitter（适配器）,TheCompilermodulethatfitsthelogicofaprojectintooneormoredevices.UsingthedatabaseupdatedbythePartitioner,theFittermatchesthelogicrequirementsoftheprojectwiththeavailableresourcesofoneormoredevices.Itassignseachlogicfunctiontothebestlogiccelllocationandselectsappropriateinterconnectionpathsandpinassignments.TheFitterattemptstomatchanyresourceassignmentsmadefortheprojectwiththeresourcesonthedevice.Ifitcannotfindafit,theFitterallowsyoutooverridesomeorallofyourassignmentsorterminatecompilation.TheFittermodulegeneratesaFitFilethatdocumentspin,buriedlogiccell,chip,clique,anddeviceassignmentsmadebytheFittermoduleinthelastsuccessfulcompilation.Eachtimetheprojectcompilessuccessfully,theFitFileisoverwritten.Youcanback-annotatetheassignmentsinthefiletopreservetheminfuturecompilations.返回,TimingSNFExtractor(时序SNF文件提取器),TheCompilermodulethatcreatesatimingSNFcontainingthelogicandtiminginformationrequiredfortimingsimulation,delayprediction,andtiminganalysis.TheTimingSNFExtractoristurnedonwiththeTimingSNFExtractorcommand(Processingmenu).ItisalsoturnedonautomaticallywhenyouturnontheEDIFNetlistWriter,VerilogNetlistWriter,orVHDLNetlistWritercommand(Interfacesmenu).TheTimingSNFExtractorcannotbeturnedonatthesametimeastheFunctionalSNFExtractorortheLinkedSNFExtractor.AtimingSNFdescribesthefullyoptimizedcircuitafteralllogicsynthesisandfittinghavebeencompleted.Regardlessofwhetheraprojectispartitionedintomultipledevices,thetimingSNFdescribesaprojectasawhole.Therefore,timingsimulationandtiminganalysis(includingdelayprediction)areavailableonlyfortheprojectasawhole.Neithertimingsimulationnorfunctionaltestingisavailableforindividualdevicesinamulti-deviceproject.Functionaltestingisavailableonlyforasingle-deviceproject.返回,Assembler（汇编器）,TheCompilermodulethatcreatesoneormoreprogrammingfilesforprogrammingorconfiguringthedevice(s)foraproject.TheAssemblermodulecompletesprojectprocessingbyconvertingtheFittersdevice,logiccell,andpinassignmentsintoaprogrammingimageforthedevice(s),intheformofoneormorePOFs,SOFs,HexFiles,TTFs,JamFiles,JBCFiles,and/orJEDECFiles.POFsandJEDECFilesarealwaysgenerated;SOFs,HexFiles,andTTFsarealwaysgeneratediftheprojectusesACEX1K,FLEX6000,FLEX8000orFLEX10Kdevices;andJamFilesandJBCFilesarealwaysgeneratedforMAX9000,MAX7000B,MAX7000AEorMAX3000Aprojects.IfyouturnontheEnableJTAGSupportoptionintheClassic&MAXGlobalProjectDeviceOptionsdialogbox(Assignmenu)ortheClassic&MAXIndividualDeviceOptionsdialogbox,theAssemblerwillalsogenerateJamFilesandJBCFilesforMAX7000AorMAX7000Sprojects.Aftercompilation,youcanalsouseSOFstocreatedifferenttypesoffilesforconfiguringFLEX6000,FLEX8000andFLEX10KdeviceswithConvertSRAMObjectFiles(Filemenu).TheprogrammingfilescanthenbeprocessedbytheMAX+PLUSIIProgrammerandtheMPUorAPUhardwaretoproduceworkingdevices.SeveralotherprogramminghardwaremanufacturersalsoprovideprogrammingsupportforAlteradevices.返回,SimulationMode,FunctionalSimulatesthebehaviorofflattenednetlistsextractedfromthedesignfiles.YoucanuseTclcommandsandscriptstocontrolsimulationandtoprovidevectorstimuli.YoucanalsoprovidevectorstimuliinaVectorWaveformFile(.vwf)oratext-basedVectorFile(.vec),althoughtheSimulatorusesonlythesequenceoflogiclevelchanges,andnottheirtiming,fromthevectorstimuli.Thistypeofsimulationalsoallowsyoutochecksimulationcoverage(theratioofoutputportsactuallytogglingbetween1and0duringsimulation,comparedtothetotalnumberofoutputportspresentinthenetlist).TimingUsesafullycompilednetlistthatincludesestimatedoractualtiminginformation.YoucanuseTclcommandsandscriptstocontrolsimulationandtoprovidevectorstimuli.YoucanalsoprovidevectorstimuliinaVectorWaveformFile(.vwf)oratext-basedVectorFile(.vec).Thistypeofsimulationalsoallowsyoutochecksetupandholdtimes,detectglitches,andchecksimulationcoverage(theratioofoutputportsactuallytogglingbetween1and0duringsimulation,comparedtothetotalnumberofoutputportspresentinthenetlist).TimingusingFastTimingModelPerformsatimingsimulationusingtheFastTimingModeltosimulatefastestpossibletimingconditionswiththefastestdevicespeedgrade,
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