《FPGA功耗优化》PPT课件

2009 Altera Corporation,Click to edit master title style,Click to edit master text styles,Second level,Third level,Fourth level,Fifth level,Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,*,2009 Altera Corporation,Altera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,and MegaCore are trademarks of Altera Corporation,Altera Confidential,Power Reduction Techniques,Altera Asia Pacific Regional Support Center,2,Agenda,Introduction,Power-Driven Synthesis,Power-Driven Fitting,Clock Power Management,Low-Power Design,Conclusion,3,Introduction,67%,22%,11%,Core Dynamic,Core Static,I/O,Dynamic Power DominantFocus of Power Optimization,99 Customer Designson Stratix II Devices,4,Dynamic Power Optimization Flow,Automatic,but less accurate,Requires testbench,more accurate,Evaluate Power,RTL,Simulation,Power-Driven Fit,Design,Power Report,Vectorless,Estimation,Hardware,Measurement,Gate-Level Simulation,+Power Analyzer,Estimate Toggle Rates,Normal,or,Extra effort,Power-Driven,Synthesis,Low Power,Design,Clock,Management,5,Power-Driven Synthesis,Located under:,“Analysis&Synthesis Settings”,6,Power-Driven Synthesis Options,Extra effort,More power reduction,May increase compile time,Normal compilation(Default),Standard power reduction,No effect on compile time or design performance,Off,No optimization,7,Power-Driven Synthesis for RAM,Memory Optimization,Normal compilation Setting,Promote Read/Write Enable Signals to Clock Read/Write Enable Signals,Extra effort Setting,Promote Read/Write Enable Signals to Clock Read/Write Enable Signals,AND,Power-Aware Memory Balancing,Memory Balancing configures RAM for optimal need,Default setting selects narrow/deeper memory configurations,e.g.4 1k x4 blocks(x4=narrow;1kwords=deeper),MW“Maximum Depth”option selects wider/shallow RAMs for power,e.g.4 256 x16 blocks(x16=wider;256words=shallow),Access only valid memory slice,disable the rest,Does require additional decoder and mux logic however,8,RAM Enable Optimization,Convert read/write enables to clock read/write enables,Shuts RAM down when unused,using,less power,Set RAM Block Type=“Auto”,Quartus II Power Optimizer chooses best RAM block configuration,RAM,Core,Read Addr,Read Data,Read En,Write Addr,Write Data,Write En,Read Clk,Write Clk,9,Memory Balancing,Power Efficient Option,16,2:4,Decoder,4 256 x16 M4K RAMs,Default Option,16,4 1k x4 M4K RAMs,1k x16 RAM,10,Maximum Depth Parameter,4k x36 Simple Dual-Port memory implementation using M4K blocks,For 128-deep M4K memory block depth,extra logic power outweighs lower memory power,Average Dynamic Power saving up to 50%,PowerPlay Power Analyzer results based on simulation,M4K Blocks Configuration with Different Memory Depth and Width,Power Saving,Best Range,11,Power-Driven Fitting,Located under:“Fitter Settings”,12,Power-Driven Fitting Options,Extra effort,Optimizes at the expense of speed and compile time,Group high-toggling logic together to minimize routing loads,Group logic from same clock domains to minimize clock routing,Runs PowerPlay Power Analyzer,Best with Value Charge Dump(.VCD)or Signal Activity(.SAF),Normal compilation,Optimizes without affecting speed or compile time,Uses power efficient DSP block configurations by swapping input operand order(transparent to designer),13,Minimize Routing Loads,Minimize capacitance of high-toggling signals,Timing constraints maintained,20 Million Toggle/s,100M Toggle/s,20M Toggle/s,100 Million Toggle/s,14,Minimize Clock Routing,Standard Place&Route,Places logic for optimal timing and routing usage,Minimizing clock power not high priority,LEs,Clocks,CLK1,CLK2,CLK3,15,Minimize Clock Routing(ctd),Extra effort Place&Route,Groups logic from same clock domain with each other,Reduces utilized clock routing(and therefore switching power),CLK1,CLK2,CLK3,Clocks,16,Power Optimization Flow(Default),Straight-forward,Longer compile times,Not fully optimized for Power,Design Entry Schematic/HDL,Power-Driven Synthesis,(Extra effort),Power-Driven Fitter,(Extra effort),PowerPlay Power Analyzer(Power Estimation),17,Power Optimization Flow(for Power),Accurate toggle rates from simulation,SAF provides design signal activity information,Processes Power Analyzer input constraints,Even longer compile times,But fully optimized for Power,Fit Design,Find Signal Toggle Rates:Gate-Level Simulation with Glitch Filtering,Signal Activity(SAF)File,Design Entry Schematic/HDL,Power-Driven Synthesis,(Extra effort),Power-Driven Fitter,(Extra effort),PowerPlay Power Analyzer(Power Estimation),18,Clock Power Management,Clocks represent a significant portion of Core Dynamic Power consumption,Clock routing power is automatically optimized by the Quartus II software where possible,Clock domains(under Power-Driven Fitting),Dynamic clock-enables driven by internal logic provides further clock routing power reduction,19,Dynamic Clock Enable,Use Enable to shut downentire clock domains,Entire clock domain unused in some cycles a